DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rusitoru et al. (US PG Pub No. 2022/0308879 A1) further in view of Coppola et al. (US PG Pub No. 2017/0206169 A1).
Rusitoru was disclosed in IDS dated 08/19/2024.
Regarding claim 1, Rusitoru teaches a method comprising:
receiving, at a system, a first virtual signal monitor request from a first virtual signal monitor associated with a first virtual signal ([0014], wherein accelerator’s physical address space is mapped into host processes virtual space; [0021], wherein an “instruction executed on the host processor and referencing a first virtual address of the process … Execution of the instruction includes translating, by translation hardware of the host processor, the first virtual address to a first physical address. However, for an instruction executed on the accelerator device and referencing the first virtual address, the first virtual address is translated to a second physical address by the translation hardware of the host processor before the instruction is sent to the accelerator device.”).
Rusitoru does not teach assigning, at hardware signal monitor circuitry (HSM) comprising a plurality of physical signal monitors, a first physical signal monitor of the plurality of physical signal monitors to the first virtual signal monitor; and in response to the first virtual signal monitor request, executing a first signal operation at the first physical signal monitor of the system.
Coppola teaches the use of a Generic Packet Processing Unit (GPPU) [hardware signal monitor] that sits between a host CPU and a coprocessor ([0077]). A user application creates a user level queue (software-side virtual structure) with an associated doorbell signal address and sends a request to the GPPU when it needs to signal the co-processor ([0078]). The GPPU maintains shadow user level queues in hardware [plurality of physical signal monitors], each including a hardware doorbell hardware signal implemented as a memory-mapped register and the GPPU assigns one of these hardware doorbell/queue structures to the software-side user level queues using hardware scheduling between different shadow user level queues ([0079-80]). Finally, the GPPU’s hardware doorbell wakes up the coprocessor and dispatches the corresponding command, i.e. executes the signal operation at the assigned physical hardware resource ([0080-81]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to assigning, at hardware signal monitor circuitry (HSM) comprising a plurality of physical signal monitors, a first physical signal monitor of the plurality of physical signal monitors to the first virtual signal monitor; and in response to the first virtual signal monitor request, executing a first signal operation at the first physical signal monitor of the system. One would be motivated by the desire to utilize Coppola’s circuity for integrating Rusitoru’s virtual to physical mappings.
Regarding claim 2, Rusitoru teaches the first signal operation comprises one of a load operation, a store operation, an atomic memory operation, and a signal wait operation ([0052]).
Regarding claim 3, Rusitoru teaches further comprising: mapping, at the HSM, a first physical signal of the system to the first virtual signal ([0028]; [0031]).
Regarding claim 4, Rusitoru teaches further comprising: in response to receiving a second virtual signal monitor request associated with a second virtual signal, forwarding, at the HSM, the second virtual signal monitor request to a memory for execution ([0042]).
Regarding claim 5, Rusitoru teaches wherein forwarding comprises forwarding the second virtual signal monitor request in response to determining at the HSM that the second virtual signal is a non-monitored signal ([0042]).
Regarding claim 6, Rusitoru teaches further comprising: in response to receiving a second virtual signal monitor request associated with a second virtual signal, forgoing execution of the second virtual signal monitor request based on an identified implication of the execution ([0042]).
Regarding claim 7, Coppola teaches further comprising: assigning, the first physical signal monitor to a second virtual signal monitor in response to determining, at the HSM, that the first physical signal monitor is to be released from the first virtual signal monitor ([0082], GPPU implementation uses hardware scheduling between different shadow user level queues which implies time-multiplexed reallocation of a finite hardware resource pool across a larger population of virtual queues).
Regarding claim 8, Rusitoru teaches wherein assigning the first physical signal monitor to the second virtual signal monitor comprises assigning, at the HSM, the first physical signal monitor to the second virtual signal monitor in response to a determination that the first virtual signal monitor has not been accessed for a threshold amount of time (Fig 3; [0028], "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312.").
Regarding claims 9-16, they are the system claims of claims 1-8 above. Therefore, they are rejected for the same reasons as claims 1-8 above.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rusitoru et al. (US PG Pub No. 2022/0308879 A1) further in view of Cornett et al. (US PG Pub No. 2020/0210359 A1).
Regarding claim 17, Rusitoru teaches a method comprising:
instantiating, at a system, a plurality of virtual signals ([0042], wherein “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware").
Rusitoru does not teach at a first time, assigning, at hardware signal monitor circuitry (HSM) of the system, a plurality of physical signals of the HSM to a first subset of the plurality of virtual signals; and at a second time, assigning, at the HSM, the plurality of physical signals to a second subset of the plurality of virtual signals.
Cornett teaches processor executed software dynamically assigns physical resources to vectors and ensures that only the vectors backed by physical resources are allocated for use by a physical of virtual function ([0014]; [0016-17]). In other words, the first subset of virtual interrupt vectors receives the finite physical vector resources. Cornett further teaches that if a virtual machine or other virtualized execution environment is migrated to another computing platform or uses another network interface, the associated vectors can be surrendered and available for use by other PFs or VFs ([0023]; [0048]). Therefore, the same physical vector resources are released from one subset of virtual functions and reassigned to a different subset at a later time.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to at a first time, assigning, at hardware signal monitor circuitry (HSM) of the system, a plurality of physical signals of the HSM to a first subset of the plurality of virtual signals; and at a second time, assigning, at the HSM, the plurality of physical signals to a second subset of the plurality of virtual signals. ne would be motivated by the desire to better utilize unused resources during migration processing as taught by Cornett.
Regarding claim 18, Rusitoru teaches wherein the second subset of the plurality of virtual signals is different from the first subset of the plurality of virtual signals ([0028], wherein "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312”; [0042], wherein “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware).
Regarding claim 19, Rusitoru teaches monitoring the plurality of physical signals at the HSM ([0028], wherein "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312”; [0042], wherein “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware).
Regarding claim 20, Rusitoru does not teach executing, at the HSM, signal operations for the plurality of physical signals in response to signal operation requests associated with the plurality of virtual signals.
However, Rusitoru teaches “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware" ([0042]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to derive executing, at the HSM, signal operations for the plurality of physical signals in response to signal operation requests associated with the plurality of virtual signals. One would be motivated by the desire to perform operations that utilize the mappings as taught by Rusitoru.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Eric C Wai/Primary Examiner, Art Unit 2195
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