DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rusitoru et al. (US PG Pub No. 2022/0308879 A1).
Rusitoru was disclosed in IDS dated 08/19/2024.
Regarding claim 1, Rusitoru teaches a method comprising:
receiving, at a system, a first virtual signal monitor request from a first virtual signal monitor associated with a first virtual signal ([0014], wherein accelerator’s physical address space is mapped into host processes virtual space; [0021], wherein an “instruction executed on the host processor and referencing a first virtual address of the process … Execution of the instruction includes translating, by translation hardware of the host processor, the first virtual address to a first physical address. However, for an instruction executed on the accelerator device and referencing the first virtual address, the first virtual address is translated to a second physical address by the translation hardware of the host processor before the instruction is sent to the accelerator device.”);
Rusitoru does not teach executing a first signal operation at hardware signal monitor circuitry (HSM) of the system.
However, Rusitoru teaches “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware" ([0042]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to derive executing a first signal operation at hardware signal monitor circuitry (HSM) of the system. One would be motivated by the desire to perform operations that utilize the mappings as taught by Rusitoru.
Regarding claim 2, Rusitoru teaches the first signal operation comprises one of a load operation, a store operation, an atomic memory operation, and a signal wait operation ([0052]).
Regarding claim 3, Rusitoru teaches further comprising: mapping, at the HSM, a first physical signal of the system to the first virtual signal ([0028]; [0031]).
Regarding claim 4, Rusitoru teaches further comprising: in response to receiving a second virtual signal monitor request associated with a second virtual signal, forwarding, at the HSM, the second virtual signal monitor request to a memory for execution ([0042]).
Regarding claim 5, Rusitoru teaches wherein forwarding comprises forwarding the second virtual signal monitor request in response to determining at the HSM that the second virtual signal is a non-monitored signal ([0042]).
Regarding claim 6, Rusitoru teaches further comprising: in response to receiving a second virtual signal monitor request associated with a second virtual signal, forgoing execution of the second virtual signal monitor request based on an identified implication of the execution ([0042]).
Regarding claim 7, Rusitoru teaches wherein the HSM includes a plurality of physical signal monitors and further comprising: assigning, at the HSM, a first physical signal monitor of the plurality of physical signal monitors, to the first virtual signal monitor (Fig 3; [0028], "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312.").
Regarding claim 8, Rusitoru teaches reassigning, at the HSM, the first physical signal monitor to a second virtual signal monitor (Fig 3; [0028], "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312.").
Regarding claims 9-16, they are the system claims of claims 1-8 above. Therefore, they are rejected for the same reasons as claims 1-8 above.
Regarding claim 17, Rusitoru teaches a method comprising:
instantiating, at a system, a plurality of virtual signals ([0042], wherein “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware").
Rusitoru does not teach at a first time assigning, at hardware signal monitor circuitry (HSM) of the system, a plurality of physical signals to a first subset of the plurality of virtual signals.
However, Rusitoru teaches "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312” ([0028]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to derive assigning, at hardware signal monitor circuitry (HSM) of the system, a plurality of physical signals to a first subset of the plurality of virtual signals. One would be motivated by the desire to perform operations that utilize the mappings as taught by Rusitoru.
Regarding claim 18, Rusitoru teaches at a second time, assigning the plurality of physical signals to a second subset of the plurality of virtual signals, the second subset different from the first subset ([0028], wherein "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312”; [0042], wherein “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware).
Regarding claim 19, Rusitoru teaches monitoring the plurality of physical signals at the HSM ([0028], wherein "A region 304 of virtual address space 214 is assigned for the code, as depicted by mapping 306. Optionally, data 206 is loaded in physical memory, as depicted by mapping 308 and mapped to virtual address region 310, as indicated by mapping 312”; [0042], wherein “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware).
Regarding claim 20, Rusitoru does not teach executing, at the HSM, signal operations for the plurality of physical signals in response to signal operation requests associated with the plurality of virtual signals.
However, Rusitoru teaches “the host mapping function sets the virtual memory overlay for the accelerator by mapping the virtual address for the input and output buffers to the physical addresses of the input and output buffers of the accelerator. This may be done, for example, by resetting a remap register value for the translation hardware" ([0042]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to derive executing, at the HSM, signal operations for the plurality of physical signals in response to signal operation requests associated with the plurality of virtual signals. One would be motivated by the desire to perform operations that utilize the mappings as taught by Rusitoru.
Conclusion
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/Eric C Wai/Primary Examiner, Art Unit 2195