DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites “two or more power states of the processor are allowed during the LPS mode”. It is unclear how you “allow” power states. One may be able to use or enable the power states. For examination purposes, “two or more power states of the processor are allowed during the LPS mode” will be read as “two or more power states of the processor are used during the LPS mode”.
Claim 10 recites “one or more other power states of the processor are prevented during the LPS mode”. It is unclear how you “prevented” power states. One may be able to not use or disable the power states. For examination purposes, “one or more other power states of the processor are prevented during the LPS mode” will be read as “one or more other power states of the processor are not used during the LPS mode”.
Claim 16 recites “two or more power states of the processor are allowed during the LPS mode”. It is unclear how you “allow” power states. One may be able to use or enable the power states. For examination purposes, “two or more power states of the processor are allowed during the LPS mode” will be read as “two or more power states of the processor are used during the LPS mode”.
Claim 16 recites “one or more other power states of the processor are prevented during the LPS mode”. It is unclear how you “prevented” power states. One may be able to not use or disable the power states. For examination purposes, “one or more other power states of the processor are prevented during the LPS mode” will be read as “one or more other power states of the processor are not used during the LPS mode”.
Claims 11-15 and 17-20 are also rejected as incorporating the deficiencies of the claims that they are dependent upon.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 10-11, 13, 16-17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jain et al. (US 20160266628).
Regarding claim 1, Jain teaches
A device comprising:
first circuitry to:
receive a first indication of a first thermal condition of a platform which comprises a processor (Fig. 1 (APU)); and (Fig. 2, [0024-25], “the STAPM controller 125 determines skin temperature, T.sub.SKIN,m, at m locations of a device housing the computing system 102 (e.g., one or more locations on the casing 145 or the display 135). As will be described in greater detail below, the skin temperature may be determined using temperature sensors 150 … block 210, the skin temperatures at the various locations are compared to a maximum skin temperature threshold, T.sub.SKIN.sub._.sub.TH (i.e., a skin temperature limit). … block 210, the skin temperatures at the various locations are compared to a maximum skin temperature threshold, T.sub.SKIN.sub._.sub.TH (i.e., a skin temperature limit).”)
transition a power management of the processor to a limited power states (LPS) mode based on the first indication, wherein two or more power states of the processor are allowed during the LPS mode, and one or more other power states of the processor are prevented during the LPS mode; and (Fig. 2 (210,215), [0025], “the skin temperatures at the various locations are compared to a maximum skin temperature threshold, T.sub.SKIN.sub._.sub.TH (i.e., a skin temperature limit). … the value of T.sub.SKIN.sub._.sub.TH may be fixed, and in some embodiments, it may be variable. The PPL represents the total power consumed by the components of the device 100 that are controlled plus those that are assumed to have fixed contributions. Within the envelope set by the PPL, various power management techniques may be employed to set the power states of the individual components, as described in greater detail below.” Wherein when step 210 is a yes, then step 215 reduces a package power limit that is limited by the default package power limit (i.e. the power states listed in Table 1 are reduced/limited because the power limit has been reduced), Table 1, [0022], “ For P0-P5, P0 represents the base DVFS state, and as the state number increases, the voltage and frequency decrease, such that P5 is the lowest DVFS state. The voltages and frequencies associated with the boost states are greater than those of the base state, P0. The boost states Pb1 and Pb1 also exhibit voltages and frequencies that decrease with index number, with Pb0 being the highest boost state.” Where the P0-P5 are maybe as part of the two or more power states of the processor allowed during LPS mode and Pb0 and Pb1 are not allowed and [0026] “the PPL is increased. In some embodiments, the PPL may be increased to a maximum defined by a thermal package power limit threshold, TPPL” where the boost states maybe be used Fig. 2 when step 201 is no and steps 220-225 are used (i.e. one or more other power states))
second circuitry which, during the LPS mode, is to:
monitor one or more software processes which are executed with the processor; and ([0016], “ A skin temperature model may incorporate activity metric based heat power estimates for the heat generating components in the device in conjunction with a thermal model of the device to estimate the skin temperature at one or more locations. The activity metrics may be correlated to heat production for different types of resources in the device, such as an advanced processing unit (APU)” and [0018], “Activity counters, such as a CPU counter 155, a GPU counter 160, and a memory counter 165 may be provided to generate device activity metrics for the components to estimate the heat they generate and how it contributes to skin temperature.” Where activity metrics of the CPU and GPU are indicative of software processes (i.e. workloads) being monitored which are running on the processors and
signal the first circuitry to transition the processor between the two or more power states based on a detection of a workload of the one or more software processes; (Fig. 2, [0022], “P0-P5 represent software visible states that may be controlled by … the STAPM controller 125” and [0053], “When determining the heat power related contribution … The STAPM controller 125 may employ the CPU counter 155 (CPU_CNT), the GPU counter 160 (GPU_CNT) and the memory counter 165 (MEM_CNT) to generate activity metrics.” And [0029], “ In the case of the APU 105, an APU power limit may be used or individual CPU and GPU power limits may be used. The reduction of a power limit in the APU 105 generally results in a transition to a lower DVFS state. In some embodiments, the power limits may be indirectly controlled by changing a frequency/P-state limits. For purposes of the present illustrative examples, the frequency/P-state limits are considered power limits.”)
wherein the first circuitry is further to:
receive a second indication of a second thermal condition of the platform; and (Fig. 2 (220), [0026], “If the minimum skin temperature at the various locations is less than the hysteresis adjusted threshold, there is thermal headroom in the system and an opportunity exists to boost system performance without exceeding the skin temperature threshold … the PPL is increased.”)
transition the processor from the LPS mode based on the second indication, wherein the first circuitry is to enable the availability of the one or more other power states. (Fig. 2 (225), [0026], “If the minimum skin temperature at the various locations is less than the hysteresis adjusted threshold, there is thermal headroom in the system and an opportunity exists to boost system performance without exceeding the skin temperature threshold … the PPL is increased. In some embodiments, the PPL may be increased to a maximum defined by a thermal package power limit threshold, TPPL” and [0031], “the DVFS states for the APU 105 may be boosted to maximize use of the total thermal capacity, a concept referred to as greedily allocating the power within the thermal budget. If the maximum skin temperature threshold is not reached, power is allocated until maximum CPU and GPU frequencies and memory bandwidth are reached.”)
Regarding claim 2, Jain teaches wherein the thermal condition is based on a skin temperature of a housing structure in which the processor is disposed. (Fig. 2, [005], “block 205, the STAPM controller 125 determines skin temperature, T.sub.SKIN,m, at m locations of a device housing the computing system 102”)
Regarding claim 6, Jain teaches wherein the one or more other power states comprise a first power state which is a high power state, relative to each of the two or more power states. (Table 1, [0022], “Table 1 below illustrates exemplary DVFS states for the CPU cores 110. P0-P5 represent software visible states that may be controlled by the operating system 135 or the STAPM controller 125, and Pb0-Pb1 represent hardware controlled boost states (not visible to software such as the operating system 135) that may be controlled by the STAPM controller 125. For P0-P5, P0 represents the base DVFS state, and as the state number increases, the voltage and frequency decrease, such that P5 is the lowest DVFS state. The voltages and frequencies associated with the boost states are greater than those of the base state, P0.”)
As to claims 10 and 16, Jain teaches these claims according to the reasoning provided in claim 1.
As to claims 11 and 17, Jain teaches these claims according to the reasoning provided in claim 2.
As to claims 13 and 19, Jain teaches these claims according to the reasoning provided in claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Yildiz et al. (US 20210034101).
Regarding claim 3, Jain teaches using skin temperature to determine a thermal condition but does not teach that the thermal condition may relate to an average skin temperature
Yildiz teaches wherein the thermal condition is an average skin temperature of the housing structure. ([0049], “a determination is made of whether the average skin temperature of any zone of the flexible display is higher than the maximum or minimum temperature constraint set for that zone. If a temperature constraint is violated, then the process continues to step 108 to take corrective actions.”)
Jain and Yildiz are analogous art. Yildiz is cited to teach a similar concept of regulating skin temperature of a device. Yildiz teaches using an average skin temperature measurements to take indicate when it is time to take corrective actions. Based on Yildiz, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Jain to use an average skin temperature to determine whether to take corrective actions. Furthermore, being able to an average skin temperature improves on Jain by being able to use less volatile measurements to determine whether to take corrective action thereby making the decision to take corrective actions more reliable. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to make the decision to take corrective actions more reliable
As to claims 12 and 18, Jain and Yildiz teaches these claims according to the reasoning provided in claim 3.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Saeidi et al. (US 11399720).
Regarding claim 4, Jain teaches using skin temperature to determine a thermal condition but does not teach that the thermal condition may relate to an integral of the skin temperature.
Saeidi teaches wherein the thermal condition is based on an integral of the skin temperature over time. (claim 1, “measuring cumulative temperature over time, wherein measuring the cumulative temperature over time includes integrating temperature values from at least one of the temperature sensors over time; comparing the cumulative temperature over time to a second temperature threshold; and in response to determining that the cumulative temperature over time exceeds the second temperature threshold, reducing power consumption of the device.”)
Jain and Saeidi are analogous art. Saeidi is cited to teach a similar concept of regulating skin temperature of a device. Saeidi teaches that using an integral of the skin temperature over time can be useful in being able to delay mitigation of the temperature to maintain performance or the device for as long as possible Based on Saeidi, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Jain to use an integral of the skin temperature over time. Furthermore, being able to an integral of the skin temperature over time improves on Jain by being able to maintain the performance of the device for as long as possible. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “such embodiments may mitigate temperature after exceeding a second threshold corresponding to cumulative temperature over time. Such embodiments may delay mitigation for as long as is desirable or practical, thereby maintaining a high level of performance and user experience before frequency throttling or voltage reduction takes place.” Col. 9, lines 35-41.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Saeidi2 et al. (US 20180011520)
Regarding claim 5, Jain teaches using skin temperature to determine a thermal condition but does not teach that the thermal condition may relate to a rate of change.
Saeidi2 teaches wherein the thermal condition is based on a rate of change of the skin temperature. ([0035], “Action 350 “Measure Tskin Ramp Rate,” includes using a skin temperature estimating algorithm that is based on temperature sensor algorithms and calculating a ramp rate for the skin temperature. The measured values at actions 320-350 may be used to calibrate the temperature mitigation algorithm and the subsequent actions.”)
Jain and Saeidi2 are analogous art. Saeidi2 is cited to teach a similar concept of regulating skin temperature of a device. Saeidi2 teaches that using the rate of change of skin temperature to determine temperature mitigation algorithms. Based on Saeidi2, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Jain to use the rate of change of the skin temperature. Furthermore, being able to use the rate of change of the skin temperature improves on Jain by being able to provide a device specific algorithm to temperature mitigation. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “The measured values at actions 320-350 may be used to calibrate the temperature mitigation algorithm and the subsequent actions.”, [0035] and “ provide for a device-specific temperature mitigation algorithm by using the physics of a particular device to set its temperature mitigation algorithm.”, [0022]
Claim(s) 7, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Kosonocky et al. (US 20210405725)
Regarding claim 7, Jain teaches wherein:
the two or more power states comprise a first power state and a second power state, wherein the first power state is a low power state, relative to the second power state; ([0022], “Table 1 below illustrates exemplary DVFS states for the CPU cores 110. P0-P5 represent software visible states that may be controlled by the operating system 135 or the STAPM controller 125, and Pb0-Pb1 represent hardware controlled boost states (not visible to software such as the operating system 135) that may be controlled by the STAPM controller 125. For P0-P5, P0 represents the base DVFS state, and as the state number increases, the voltage and frequency decrease, such that P5 is the lowest DVFS state. The voltages and frequencies associated with the boost states are greater than those of the base state, P0. The boost states Pb1 and Pb1 also exhibit voltages and frequencies that decrease with index number, with Pb0 being the highest boost state.”)
Jain does not teach but Kosonocky teaches
the first circuitry is to transition the processor from the first power state to the second power state based on the detection of the workload; and the first circuitry is further to transition the processor from the second power state to the first power state based on a completion of the workload. ([0016], “If the processing workload is too high at the current clock frequency, then it increases the P-state to increase the clock frequency and increase performance. Conversely if the processing workload is too low at the current clock frequency, then it decreases the P-state to decrease the clock frequency and save power.”)
Jain and Kosonocky are analogous art. Kosonocky is cited to teach a similar concept of power management. Kosonocky teaches increasing the power state to perform a workload/activity and decreasing a power state there is no workload/activity. Based on Kosonocky, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Jain to increase the power state to perform a workload/activity and decreasing a power state there is no workload/activity. Furthermore, being able to increase the power state to perform a workload/activity and decreasing a power state there is no workload/activity improves on Jain by being able to increase performance when needed and reduce power consumption when not. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “If the processing workload is too high at the current clock frequency, then it increases the P-state to increase the clock frequency and increase performance. Conversely if the processing workload is too low at the current clock frequency, then it decreases the P-state to decrease the clock frequency and save power.”, [0016]
As to claims 14 and 20, Jain and Kosonocky teaches these claims according to the reasoning provided in claim 7.
Claim(s) 8-9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Wen et al. (US 10147464)
Regarding claim 8, Jain teaches switching between a first and second plurality of power states but does not specifically teach using two state machines to control them. ([0022], “ For P0-P5, P0 represents the base DVFS state, and as the state number increases, the voltage and frequency decrease, such that P5 is the lowest DVFS state. The voltages and frequencies associated with the boost states are greater than those of the base state, P0. The boost states Pb1 and Pb1 also exhibit voltages and frequencies that decrease with index number, with Pb0 being the highest boost state.” Where the P0-P5 are the second plurality power states of the processor allowed during LPS mode and Pb0, Pb1, and P0-P5 are the first plurality of power states.
Jain teaches a total number of the first plurality of power states is greater than a total number of the second plurality of power states.
Wen teaches
wherein: the first circuitry to transition the power management of the processor to the LPS mode comprises the first circuitry to transition from a first state machine to a second state machine; the first state machine facilitates transitions of the processor between any of a first plurality of power states; the second state machine facilitates transitions of the processor between any of a second plurality of power states; and (col. 7, lines 9-26, “Power management circuit 20 in the embodiment shown also includes power state controller 210. This circuit block may be the decision making block in determining into which performance state the various functional circuit blocks are placed during operation. Power state controller 210 in the embodiment shown is coupled to receive the various performance related signals (Perf1, Perf2, Perf3) from their corresponding units as discussed above. As previously noted, these signals may include requests, e.g., for a performance state change or placement into a sleep state. The performance related signals may also include signals indicative of, e.g., a sensed temperature, power consumption, workload demand, or other metric of the corresponding functional circuit block from which received. Power state controller 210 may be implemented in one embodiment as one or more state machines to determine which performance state in which a particular functional circuit block is to operate.”)
Jain and Wen are analogous art. Wen is cited to teach a similar concept of power management using performance states. Wen teaches a known technique of using two state machines to determine performance state of operation of a device in two distinct modes. Both Jain and Wen teach controlling performance states but Jain does not specifically teach using state machines to control the performance states while Wen does. Based on Wen and the KSR rationale of using of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Jain to use two state machines for the two separate power modes of operation of full performance and lower power performance.
Regarding claim 9, Jain teaches wherein the second plurality of power states is a subset of the first plurality of power states. ([0022], “ For P0-P5, P0 represents the base DVFS state, and as the state number increases, the voltage and frequency decrease, such that P5 is the lowest DVFS state. The voltages and frequencies associated with the boost states are greater than those of the base state, P0. The boost states Pb1 and Pb1 also exhibit voltages and frequencies that decrease with index number, with Pb0 being the highest boost state.” Where the P0-P5 are the second plurality power states of the processor allowed during LPS mode and Pb0, Pb1, and P0-P5 are the first plurality of power states.
As to claim 15, Jain and Wen teaches this claim according to the reasoning provided in claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p.
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 August 2, 2026
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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