DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0045] recites “ESD discharge current paths for a negative CDM stress are indicated by arrows 124, 126 and 128.” It is unclear how diode DP1 conducts for a negative CDM stress? Examiner interprets the above recitation as --ESD discharge current paths for a positive CDM stress are indicated by arrows 124, 126 and 128.--. Several instances of “negative CDM stress” is found throughout the specification, which requires appropriate correction.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 9-12 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ker (M. -d. Ker, "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology," 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications, Kos, Greece, 2006, pp. 217-279).
Regarding claim 1, Ker teaches an integrated circuit (IC) device (page 263, using the additional ESD bus for the IC with power-down-mode application) comprising:
a conductive contact (e.g. I/O pad, fig.7.41) at a surface of the IC device (page 264, The ESD current at the I/O pad under PS-mode ESD stress) and coupled with first circuitry (e.g. internal circuits, fig.7.41);
a first supply line (i.e. VDD, fig.7.41) and a second supply line (i.e. VSS, fig.7.41) to provide power to the first circuity (e.g. VDD and VSS are connected to internal circuits, fig.7.41), the first supply line coupled with the first circuitry to provide a first voltage (page 244, applied 8-V voltage pulse), and the second supply line coupled with the first circuitry to provide a second voltage (page 244, the VSS grounded);
second circuitry (e.g. circuitry comprising Second power-rail ESD clamp circuit, fig.7.41) coupled with the conductive contact (e.g. coupled to I/O pad via Dp and Dn, fig.7.41), the second circuitry further coupled with the second supply line (e.g. coupled to VSS, fig.7.41) and a third supply line (e.g. ESD Bus, fig.7.41), the third supply line to provide a third voltage (page 263, The ESD bus is not directly connected to an external power pin, but biased to VDD); and
a resistive element (e.g. resistive component of diode D1, fig.7.41) coupled between the first supply line and the third supply line (page 263, The diode DI connected between the VDD power line and ESD bus).
Regarding claim 2, Ker teaches the IC device of claim 1, wherein the second circuitry comprises a first diode (i.e. diode Dp, fig.7.41) coupled between the conductive contact and the third supply line (e.g. coupled between I/O pad and ESD Bus, fig.7.41), a second diode (i.e. diode Dn, fig.7.41) coupled between the conductive contact and the second supply line (e.g. coupled between I/O pad and VSS, fig.7.41), and a power clamp (i.e. Second power-rail ESD clamp circuit, fig.7.41) coupled between the third supply line and the second supply line (e.g. coupled between ESD Bus and VSS, fig.7.41).
Regarding claim 3, Ker teaches the IC device of claim 2, wherein the first circuitry comprises at least one of a switch (page 218, the MOS devices).
Regarding claim 4, Ker teaches the IC device of claim 1, wherein the second circuitry comprises first electrostatic discharge (ESD) protection circuitry (e.g. circuitry comprising Second power-rail ESD clamp circuit, fig.7.41), further comprising second ESD protection circuitry (e.g. circuitry comprising First power-rail ESD clamp circuit, fig.7.41) coupled with the conductive contact (e.g. coupled via D1, Dp and Dn, fig.7.41), and coupled between the first supply line and the second supply line (e.g. coupled between VDD and VSS, fig.7.41).
Regarding claim 9, Ker teaches the IC device of claim 1, the IC device further comprising:
third circuitry (e.g. circuitry comprising First power-rail ESD clamp circuit, fig.7.41); and
a plurality of conductive interconnects to deliver power to the third circuitry (e.g. conductive interconnects between VDD and First power-rail ESD clamp circuit, between D1 and VDD and between VSS and First power-rail ESD clamp circuit, fig.7.41), wherein the resistive element comprises the plurality of conductive interconnects (e.g. conductive interconnect between D1 and VDD, fig.7.41).
Regarding claim 10, Ker teaches the IC device of claim 1, wherein the resistive element comprises a feature having a resistance value of at least 500 ohms (it is necessarily true that a reverse biased diode acts as open circuit with resistance greater than 500 ohms).
Regarding claim 11, Ker teaches the IC device of claim 1, wherein the only coupling between the first supply line and the third supply line is the resistive element (e.g. diode D1, fig.7.41).
Regarding claim 12, Ker teaches the IC device of claim 1, wherein the second voltage is a ground reference voltage (page 264, grounded VSS) and the third voltage is a local supply voltage (page 263, The ESD bus is not directly connected to an external power pin, but biased to VDD through the diode DI).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ker (M. -d. Ker, "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology," 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications, Kos, Greece, 2006, pp. 217-279), and further in view of Smith (US 20040136126 A1).
Regarding claim 5, Ker teaches the IC device of claim 4.
Ker does not teach, wherein the second ESD protection circuitry comprises a first diode coupled between the conductive contact and the first supply line, a second diode coupled between the conductive contact and the second supply line, and a power clamp coupled between the first supply line and the second supply line.
Smith teaches in a similar field of endeavor of ESD power rail clamp circuits, a first diode coupled between a conductive contact and a first supply line (e.g. diode between I/O pad and VDD, fig.3), a second diode coupled between the conductive contact and a second supply line (e.g. diode between I/O pad and VSS, fig.3), and a power clamp coupled between the first supply line and the second supply line (e.g. Rail clamp between VDD and VSS, fig.3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the second ESD protection circuitry comprising a first diode coupled between the conductive contact and the first supply line, a second diode coupled between the conductive contact and the second supply line, and a power clamp coupled between the first supply line and the second supply line in Ker, as taught by Smith, as it provides the advantage of robust protection of the power rails from ESD while reducing the effects of parasitic bus resistance.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ker (M. -d. Ker, "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology," 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications, Kos, Greece, 2006, pp. 217-279), and further in view of Krishnamoorthy (US 20220416536 A1).
Regarding claim 8, Ker teaches the IC device of claim 1, wherein the conductive contact is a first conductive contact (i.e. I/O pad, fig.7.41), further comprising:
a second conductive contact (e.g. contact between VDD and power supply, figs.7.41 and 7.6) on the surface of the IC device (page 223, VDD or VSS pins), wherein the first supply line is coupled with the second conductive contact (e.g. it is necessarily true that VDD of fig.7.41 is coupled to VDD pin of fig.7.5);
a third conductive contact (e.g. contact between ESD Bus and D1, fig.7.41), wherein the third supply line is coupled with the third conductive contact (e.g. it is necessarily true that ESD Bus and contact to D1 are coupled, fig.7.41); and
wherein the resistive element comprises at least one of the second conductive contact and the third conductive contact (e.g. contact of D1 at ESD Bus, fig.7.41).
Ker does not teach, the third conductive contact on the surface of the IC device.
Krishnamoorthy teaches in a similar field of endeavor of ESD circuit for multi-voltage rails, a third conductive contact on the surface of the IC device ([0032], Multiple rails may be provided to carry current to or from the power supply).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the third conductive contact on the surface of the IC device in Ker, as taught by Krishnamoorthy, as it provides the advantage of implementing each rail using one or more wires, connectors, interconnects, traces or like, providing flexibility of design.
Allowable Subject Matter
Claims 14-20 are allowed.
Claims 6-7 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Ker (M. -d. Ker, "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology," 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications, Kos, Greece, 2006, pp. 217-279) teaches the IC device of claim 1, wherein the resistive element is a first resistive element (e.g. resistive component of diode D1, fig.7.41) and the second circuitry is first electrostatic discharge (ESD) protection circuitry (e.g. circuitry comprising Second power-rail ESD clamp circuit, fig.7.41).
Ker does not teach, further comprising: second ESD protection circuitry coupled with the conductive contact, the second ESD protection circuitry coupled with the second supply line and a fourth supply line, the fourth supply line to provide a fourth voltage and to provide a path to the second supply line for a current associated with an ESD event in the fourth supply line; and a second resistive element coupled between the first supply line and the fourth supply line, the second resistive element to reduce a current in the first supply line resulting from the current associated with an ESD event in the fourth supply line.
Prior art Smith (US 20040136126 A1), Zhu (US 20230009631 A1), Krishnamoorthy (US 20220416536 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “second ESD protection circuitry coupled with the conductive contact, the second ESD protection circuitry coupled with the second supply line and a fourth supply line, the fourth supply line to provide a fourth voltage and to provide a path to the second supply line for a current associated with an ESD event in the fourth supply line; and a second resistive element coupled between the first supply line and the fourth supply line, the second resistive element to reduce a current in the first supply line resulting from the current associated with an ESD event in the fourth supply line.”
Claim 7 is indicated as allowable, as it depends on allowable claim 6.
Regarding claim 13, Ker (M. -d. Ker, "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology," 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications, Kos, Greece, 2006, pp. 217-279) teaches the IC device of claim 1.
Ker does not teach, wherein the first voltage is a ground reference voltage and the third voltage is a local ground reference voltage.
Prior art Smith (US 20040136126 A1), Zhu (US 20230009631 A1), Krishnamoorthy (US 20220416536 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the first voltage is a ground reference voltage and the third voltage is a local ground reference voltage.”
Regarding claim 14, Bandaru (US 20210384723 A1) teaches a system (abstract, An electrostatic discharge (ESD) circuit) comprising:
a microprocessor ([0023], microprocessors);
a memory coupled with the microprocessor ([0023], storage devices);
an integrated circuit (IC) device coupled with at least one of the memory or the microprocessor ([0023], ICs).
Ker (M. -d. Ker, "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology," 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications, Kos, Greece, 2006, pp. 217-279) substantially teaches all other limitations of the IC device as discussed above in claim 1.
Bandaru and Ker do not teach, the resistive element to reduce a current in the first supply line resulting from the current associated with an ESD event in the third supply line.
Prior art Smith (US 20040136126 A1), Zhu (US 20230009631 A1), Krishnamoorthy (US 20220416536 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “the resistive element to reduce a current in the first supply line resulting from the current associated with an ESD event in the third supply line.”
Claims 15-17 are allowed as they depend on allowed claim 14.
Regarding claim 18, Ker (M. -d. Ker, "ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology," 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications, Kos, Greece, 2006, pp. 217-279) substantially teaches the limitations as stated above in claim 1.
Ker does not teach, the resistive element to reduce a current in the first supply line resulting from the current associated with an ESD event in the local supply line.
Prior art Smith (US 20040136126 A1), Zhu (US 20230009631 A1), Krishnamoorthy (US 20220416536 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “the resistive element to reduce a current in the first supply line resulting from the current associated with an ESD event in the local supply line.”
Claims 19-20 are allowed as they depend on allowed claim 18.
Conclusion
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/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 07/31/2026
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