DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is sent in response to Applicant’s Communication received 6/29/2023 for application number 18/216,456. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and claims.
Claims 1 – 20 are presented for examination.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner believes that the title of the invention is imprecise. A descriptive title indicative of the invention will help in proper indexing, classifying, searching, etc. See MPEP 606.01. However, the title of the invention should be limited to 500 characters.
Claim Objections
Claims 11-15 are objected to because of the following informalities: Claim 11-15 recite “The one or more computer-readable storage media” but it appears Applicant meant “The one or more non-transitory computer-readable storage media”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, 8, 10-11, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johns et al. (hereinafter as Johns) PGPUB 2007/0124622, and further in view of Dai et al. (hereinafter as Dai) PGPUB 2020/0089308.
As per claim 1, Johns teach a processor [claim 18 or 0036: (BE Chip 300 is a single-chip multiprocessor having multiple synergistic processor units (SPU)s 310, 311, 312, etc.)] comprising:
first circuitry [0067: thermal management control unit 402] to:
identify a threshold limit based on an indication of a performance constraint [0065 and 0068: (numeric value representing the temperature (indication of a performance constraint) is received, and a programmable throttle point is identified (threshold limit); the indication is then compared to the threshold limit) or 0068 and 00159: (programmable throttle point (threshold limit) is set as the operation of hysteresis thermal throttling (performance constraint) begins)];
provide the threshold limit to each of multiple cores of a processor module [0098 and 0164: (thermal management throttle point register sets the throttle temperature point for sensors of each SPU in the processor chip 300 (threshold limit to each of multiple cores of a processor module))];
receive multiple indications each from a different respective one of the multiple cores, wherein, for each core of the multiple cores, a respective one of the multiple indications identifies whether the core violates a current test criteria which is based on the threshold limit [0062 and 0065: (one sensor is located in each of the SPEs (cores) or SPUs to track its temperature, and feedback from each of the sensors are monitored), and 0076, 0083, and 0016: (temperatures from each of the thermal sensors on each SPE/core are received; determines when current temperature of a sensor is equal to or greater than the throttle temperature (violates a current test criteria))]; and
based on each of the multiple indications, detect an instance of a single violation condition wherein one core of the multiple cores violates the current test criteria [0098, 0101, and 0164: (throttle point for each SPE are set independently and thus it is logical that some SPE could violate the temperature criterion while other SPE do not)]; and
second circuitry coupled to the first circuitry, wherein, based on the instance of the single violation condition, the second circuitry is to throttle an execution of instructions with the one of the multiple cores [0098: (Execution throttling of SPE starts when the temperature is equal or above the throttle point) and FIG. 4: (throttling logic 418 (second circuitry) is coupled to TMCU 402 (first logic)].
Johns does not explicitly teach wherein each of the multiple cores is to receive a first supply voltage, and wherein each of the multiple cores is to receive a first clock signal; based on each of the multiple indications, detect an instance of a single violation condition wherein one core of the multiple cores violates the current test criteria, while each other core of the multiple cores satisfies the current test criteria; wherein the second circuitry is to throttle the execution while the multiple cores is maintained in a first power state.
Dai teaches a multi-core processor that monitors for thermal constraints or violations using thermal sensors [0023, 0033, and 0109]. Dai is thus similar to Johns and monitors the thermal temperature for the multi-core processor. Dai further teaches wherein each of the multiple cores is to receive a first supply voltage, and wherein each of the multiple cores is to receive a first clock signal [0031: (each core receives a voltage from IVR and as such, can operate at independent voltage and frequency; frequency is indicative of a clock, and thus each core receive a clock signal) and 0135: clocks]; based on each of the multiple indications, detect an instance of a single violation condition wherein one core of the multiple cores violates the current test criteria, while each other core of the multiple cores satisfies the current test criteria [FIG. 20 and 0143: (only a core0 incurs local violations; other cores1-N thus do not incur violations)]; wherein the second circuitry is to throttle the execution while the multiple cores is maintained in a first power state [FIG. 20, 0024, and 0143: (only a core0 that incurs local violations may be throttled; thus other cores1-N that do not incur violations are not throttled)].
The combination of Johns with Dai leads to Johns’ multicore processor having cores that each receive voltage and clock signals independently, and only throttling the one core that violates a condition and not throttling the other cores that do not violate a condition.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Dai’s teachings of having independent voltage and clock frequency to each core in the multicore processor in Johns, and to throttle only one core that violate a condition but not other cores in Johns. Dai teaches the specific example in Johns in which only one core violates a constraint while the other cores do not, and as a result, only the core in violation is throttled. One of ordinary skill in the art would have been motivated to having independent voltage and clock frequency to each core in the multicore processor in Johns because it allows for greater flexibility and performance on each core. One of ordinary skill in the art would have been motivated to only throttle the core in violation of a constraint but not the other cores that have no violation in Johns because it would be much more effective in controlling the violation without punishing other cores and causing a reduction in performance.
As per claim 2, Johns and Dai teach the processor of claim 1, wherein the performance constraint comprises a threshold maximum variance of a performance metric from a target value [Johns 0065, 0068, 0095, and 0157: (programmable detected hysteresis range)].
As per claim 5, Johns and Dai teach the processor of claim 1, wherein the second circuitry to throttle the execution of instructions comprises the second circuitry to signal the one core of the multiple cores to squash pulses of the first clock signal to generate a modified version of the first clock signal [Dai 0135: (operation may be throttled by squashing some number of clock signals)].
As per claim 8, Johns and Dai teach the processor of claim 1, wherein the multiple indications are first indications [Johns 0062 and 0065 and FIG. 3 and FIG. 4: (sensors are distributed across different SPEs and indications are received from those sensors about the SPEs/cores; first indications may be from DTS of SPUs of SPE 302 and SPE 303)]; receive second indications each from a different respective one of the multiple cores [Johns 0062 and 0065 and FIG. 3 and FIG. 4: (sensors are distributed across different SPEs/SPUs; second indications may be from DTS of SPE 304 and PPE 301)], wherein, for each core of the multiple cores, a respective one of the second indications identifies whether the core violates the current test criteria which is based on the threshold limit [Johns 0062 and 0065: (sensor is located in each of the SPEs (cores) or SPUs to track its temperature, and second feedback from each of the sensors of SPE 304 and PPE 301 are monitored), and 0076, 0083, and 0016: (temperatures from each of the thermal sensors on each PPE/SPE/core are received; determines when current temperature of a sensor is equal to or greater than the throttle temperature (violates a current test criteria))]; based on each of the second indications, detect an instance of a multiple violation condition wherein two or more of the multiple cores each violates the current test criteria [Johns 0068-0069: (determines if second indication temperatures are equal or above the throttle point of the corresponding SPE 304 and PPE 301)]; and based on the instance of the multiple violation condition, cause the multiple cores to transition from the first power state to a second power state [Johns 0069: (each PPE or SPE may be throttled independently) and Dai 0026 and 0144: (throttle happens only to those circuits/cores that exceed their budget); (DTS sensor readings of SPE 304 and PPE 301 are also monitored and may be considered second indications, and when their sensor readings both surpass their corresponding throttle point, they may both be throttled from a first power state to a lower/second power state)].
Claim 10 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim 11 is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Claim 15 is similar in scope to claim 8 as addressed above and is thus rejected under the same rationale.
Claim 16 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale. Johns further teaches a memory to store multiple instructions which are to be executed in a sequence [0178 and claim 14]; a processor coupled to the memory [0178 and claim 14]. Dai also teaches it [0175].
Claim 17 is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Claim(s) 3, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johns et al. (hereinafter as Johns) PGPUB 2007/0124622 in view of Dai et al. (hereinafter as Dai) PGPUB 2020/0089308, and further in view of Svilan et al. (hereinafter as Svilan) PGPUB 2013/0275782.
As per claim 3, Johns and Dai teach the processor of claim 1.
Johns and Dai do not teach wherein the threshold limit is a threshold maximum dynamic capacitance level. Johns and Dai seem to focus on temperature levels rather than a dynamic capacitance level.
Svilan teaches power gating a multi-core processor to conserve power. Svilan is thus similar to Johns and Dai. Svilan further teaches wherein the threshold limit is a threshold maximum dynamic capacitance level [0038, 0051, 0053, 0064, and 0067: (maximum dynamic capacitance is determined, and power gate circuitry is controlled based on the dynamic capacitance)]. Svilan teaches setting power gating points based on the dynamic capacitance.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Svilan’s teachings of using dynamic capacitance levels as threshold points in Johns and Dai. One of ordinary skill in the art would have been motivated to set threshold limits and throttling points based on dynamic capacitance levels in Johns and Dai because managing the dynamic capacitance level reduces the power consumption, the thermal and heat generation, the battery life, and the switching speeds in transistor circuits, thus improving overall operation.
Claim 12 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Claim 18 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Claim(s) 4, 6, 13, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johns et al. (hereinafter as Johns) PGPUB 2007/0124622 in view of Dai et al. (hereinafter as Dai) PGPUB 2020/0089308, and further in view of Garg et al. (hereinafter as Garg) PGPUB 2022/0100247.
As per claim 4, Johns and Dai teach the processor of claim 1.
Johns and Dai do not teach wherein the second circuitry to throttle the execution of instructions comprises the second circuitry to provide a bubble in an instruction pipeline of the one core of the multiple cores.
Garg teaches power management in a computing device and a particular power state with only one core placed in such a state. Garg is thus similar to Johns and Dai because they teach placing only one core in a different power state. Garg further teaches wherein the second circuitry to throttle the execution of instructions comprises the second circuitry to provide a bubble in an instruction pipeline of the one core of the multiple cores [0191: (upon receiving a soft throttle, bubbles are injected in the pipeline to reduce effective current draw for the cores)]. Garg teaches a particular throttling method to reduce power usage in a computing device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Garg’s teachings of providing bubbles in the pipeline to throttle execution in Johns and Dai. One of ordinary skill in the art would have been motivated to provide bubbles in the pipeline as a way to perform throttling in Johns and Dai because it is a gentler and more gradual way of reducing power draw compared to a hard and fast throttling in which cores are stopped, thereby allowing for reducing of power draw while providing performance.
As per claim 6, Johns and Dai teach the processor of claim 1.
Johns and Dai do not explicitly teach wherein the second circuitry to throttle the execution of instructions comprises the second circuitry to signal the one core of the multiple cores to stretch pulses of the first clock signal to generate a modified version of the first clock signal.
Garg teaches power management in a computing device and a particular power state with only one core placed in such a state. Garg is thus similar to Johns and Dai because they teach placing only one core in a different power state. Garg further teaches wherein the second circuitry to throttle the execution of instructions comprises the second circuitry to signal the one core of the multiple cores to stretch pulses of the first clock signal to generate a modified version of the first clock signal [0160, 0185, and 0191: (soft throttle by stretching the clock to lower frequency)]. Garg teaches a particular throttling method to reduce power usage in a computing device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Garg’s teachings of stretching clock signals to throttle execution in Johns and Dai. One of ordinary skill in the art would have been motivated to stretch clock signals as a way to perform throttling in Johns and Dai because it is a gentler and more gradual way of reducing power draw compared to a hard and fast throttling in which cores are stopped, thereby allowing for reducing of power draw while providing performance.
Claim 13 is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Claim 19 is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Claim(s) 7, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johns et al. (hereinafter as Johns) PGPUB 2007/0124622 in view of Dai et al. (hereinafter as Dai) PGPUB 2020/0089308, and further in view of Burns et al. (hereinafter as Burns) PGPUB 2014/0359328.
As per claim 7, Johns and Dai teach the processor of claim 1.
Johns and Dai do not teach wherein the second circuitry to throttle the execution of instructions comprises the second circuitry to signal the one core of the multiple cores to slow an instruction fetch unit of the one core of the multiple cores.
Burns teaches monitoring real time power and temperature data of processors and making adjustments as needed to reduce power consumption. Burns is thus similar to Johns and Dai. Burns further teaches wherein the second circuitry to throttle the execution of instructions comprises the second circuitry to signal the one core of the multiple cores to slow an instruction fetch unit of the one core of the multiple cores [0018, 0030, and 0041: (limit current consumption of the core by throttling the fetch unit)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Burns’ teachings of throttling the fetch unit to throttle execution in Johns and Dai. One of ordinary skill in the art would have been motivated to throttle the fetch unit as a way to perform throttling in Johns and Dai because it is a way to reduce power consumption without turning off components and then needing to turn them on later, thereby allowing for a faster and easier transition between power states.
Claim 14 is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Claim 20 is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johns et al. (hereinafter as Johns) PGPUB 2007/0124622 in view of Dai et al. (hereinafter as Dai) PGPUB 2020/0089308, and further in view of Ganpule et al. (hereinafter as Ganpule) PGPUB 2015/0177824.
As per claim 9, Johns and Dai teach the processor of claim 1, wherein: the processor module is a first processor module [Dai FIG. 15: (processor 1570)]; the multiple cores is a first multiple cores [Dai FIG. 15: (multiple processor cores 1574a, 1574b)]; the processor further comprises a second processor module which comprises a second multiple cores [Dai FIG. 15 processor 1580 which has multiple cores 1584a and 1584b)].
Johns and Dai do not explicitly teach each of the second multiple cores receives a second supply voltage, and wherein each of the second multiple cores receives a second clock signal; and the second multiple cores are to be maintained in a second power state while the execution of instructions with the one of the multiple cores is throttled.
Ganpule also teaches a plurality of processors having multiple cores [FIG. 8 processor 670 and processor 680]. Ganpule is similar to Johns and Dai because they teach multiple multi-core processors. Ganpule further teaches each of the second multiple cores receives a second supply voltage, and wherein each of the second multiple cores receives a second clock signal [0065: (each of the multi-core processors can provide independent operating voltages and clock signals)]; the second multiple cores are to be maintained in a second power state while the execution of instructions with the one of the multiple cores is throttled [0024, 0042, 0045 0089: (each core may be independent power domain and may enter or exit states based on workload; thus some cores of another multi-core processor may be maintained at a power state while another core is throttled)]. Ganpule thus teaches providing different voltage and clock signals to a second multi-core processor than a first multi-core processor, and also teaches that cores in the second multi-core processor may each be independently throttled or maintained in a particular power state.
The combination of Johns and Dai with Ganpule allows Johns and Dai’s different multi-core processors to run independently at different voltages and currents.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Ganpule’s teachings of providing different voltage and clock to different multi-core processors in Johns and Dai, and let cores in the different multi-core processors to be throttled or maintained in a power state independently. One of ordinary skill in the art would have been motivated to provide independent clocks and voltages to different multi-core processors in Johns and Dai because it allows for greater independence between processor devices and greater reliability by not relying on just a single voltage and clock. One of ordinary skill in the art would have been motivated to allow cores on the second multi-core processor to also be throttled or maintained in a power state independent of other cores on that processor (such as in the case with the first multi-core processor) because it allows for flexibility and greater power control of processing elements that leads to better performance and power savings.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Narayanaswamy et al. (PGPUB 2024/0094796) teaches setting threshold values based on inputs associated with a processor such as dynamic capacitance.
Augustine et al. (PGPUB 2020/0081512) teaches gating processor core clock to save dynamic capacitance.
Heilper et al. (PGPUB 2019/0369696) teaches Cdyn_max and guiding power allocation based on it.
Ananthakrishnan et al. (PGPUB 2018/0059757) teaches determining a frequency based at least in part on the particular dynamic capacity [0168].
Burr (PGPUB 2016/0094849) teaches requesting cores to modify their frequency, power, operating current, or dynamic capacitance [0019].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
