DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Andrys et al (Fig. 5); 9,698,853].
Regarding claim 1, Andrys et al discloses an amplifier circuit comprising a variable voltage source (520) configured to generate a first voltage (output voltage signal of 520) which varies in response to a variable current (the current source in 520), an amplifier (530) comprising a first input terminal (- input terminal of 530) to which the first voltage (output voltage signal of 520) is applied, and a limit current source (404) connected to a second input terminal (+ input terminal of 530) of the amplifier (530) and configured to generate a limit current (Ib_clamp) corresponding to the first voltage (output voltage signal of 520).
Regarding claim 16, Andrys et al discloses an amplifier circuit comprising a variable voltage source (520) configured to generate a first voltage (output voltage signal of 520) which varies in response to a variable current (the current source in 520), an amplifier (530) comprising a first input terminal (- input terminal of 530) to which the first voltage (output voltage signal of 520) is applied, and a limit current source (404) configured to generate a limit current (the current flowing out of the drain terminal of the transistor 512) corresponding to the first voltage (output voltage signal of 520), and apply a voltage (voltage present at the drain terminal of the transistor 512) corresponding to the limit current (the current flowing out of the drain terminal of the transistor 512) to a second input terminal (+ input terminal of 530) of the amplifier (530).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 7-9 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over [Andrys et al (Fig. 5); 9,698,853] in view of [Ohta et al (Fig. 2); 8,183,925].
Regarding claims 2 and 17, Andrys et al discloses all the limitations in claim 2 as described above except for the internal structure of the variable voltage source. Ohta et al discloses an amplifier circuit comprising the variable voltage source (420b) comprises a first transistor (422b) and a second transistor (423b) connected to each other in a current mirror configuration, a variable current source (421b) connected between a first terminal (drain terminal of the transistor 422b) of the first transistor (422b) and a ground (ground) and configured to generate the variable current, and a first resistor (424b) connected between a first terminal (drain terminal of the transistor 423b) of the second transistor (423b) and the ground (ground). It would have been obvious to substitute Ohta et al’s variable voltage source (420b in Fig. 2 of Ohta et al) in place of Andrys et al’s variable voltage source (520 in Fig. 5 of Andrys et al) since Andrys et al discloses a generic variable voltage source thereby suggesting that any equivalent variable voltage source would have been usable in Andrys et al’s reference.
Regarding claims 3 and 18, wherein a voltage of the first terminal (drain terminal of the transistor 423b) of the second transistor (423b) is the first voltage (output voltage signal of 520).
Regarding claim 4, wherein the limit current source (404) is connected to an output terminal (output terminal of 530) of the amplifier (530), and a voltage of the output terminal (output terminal of 530) of the amplifier (530) is a second voltage (output voltage of 530) that varies in response to the variable current (the current source in 520).
Regarding claims 5 and 19, wherein the limit current source (404) comprises a first transistor (512) comprising a control terminal (gate terminal of 512) to which the second voltage (output voltage of 530) is applied, a first terminal (drain terminal of the transistor 512) connected to the second input terminal (+ input terminal of 530) of the amplifier (530), a first resistor (513) connected between the first terminal (drain terminal of the transistor 512) of the first transistor (512) and a ground (ground), and a second transistor (511a) comprising a control terminal (gate terminal of the transistor 511a) to which the second voltage (output voltage signal of 530) is applied and a first terminal (drain terminal of the transistor 511a) which outputs the limit current (Ib_clamp).
Regarding claim 7, wherein the limit current (Ib_clamp) varies in response to the first voltage (output voltage signal of 520) and the second voltage (output voltage of 530).
Regarding claim 8, wherein the limit current (Ib_clamp) is generated to be supplied to a bias circuit configured to bias a power transistor (PA FINAL STAGE).
Regarding claim 9, wherein the amplifier (530) is an operational amplifier and the first input terminal (- input terminal of 530) of the amplifier (530) is an inverting terminal of the operational amplifier (530), and the second input terminal (+ input terminal of 530) of the amplifier (530) is a non-inverting terminal of the operational amplifier (530).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over [Kocer et al (Fig. 1); 8,319,560] in view of [Andrys et al (Fig. 5); 9,698,853].
Kocer et al discloses an amplifier circuit comprising a power transistor (14), a bias circuit (18) configured to supply a bias current (output signal of 18) to the power transistor (14), and an overcurrent protection circuit (16) configured to supply a limit current (output signal of 16) to the bias circuit (18) to prevent an overcurrent from flowing in the power transistor (14). As described above, Kocer et al discloses all the limitations in claim 10 except for that the internal structures of the overcurrent protection circuit. Andrys et al discloses an amplifier circuit comprising a variable voltage source (520) configured to generate a first voltage (output voltage signal of 520) which varies in response to a variable current (the current source in 520), an amplifier (530) comprising a first input terminal (- input terminal of 530) to which the first voltage (output voltage signal of 520) is applied, and a limit current source (404) connected to a second input terminal (+ input terminal of 530) of the amplifier (530) and configured to generate a limit current (Ib_clamp) corresponding to the first voltage (output voltage signal of 520). It would have been obvious to substitute Andrys et al’s overcurrent protection circuit in place of Kocer et al’s overcurrent protection circuit (16 in Fig. 1 of Kocer et al) since Kocer et al discloses a generic overcurrent protection circuit thereby suggesting that any equivalent overcurrent protection circuit would have been usable in Kocer et al’s reference.
Claim(s) 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over [Kocer et al (Fig. 1); 8,319,560] in view of [Andrys et al (Fig. 5); 9,698,853] in further view of [Ohta et al (Fig. 2); 8,183,925].
Regarding claim 11, Kocer et al in view of Andrys et al discloses all the limitations in claim 11 except for that the internal structures of the variable voltage source. Ohta et al discloses an amplifier circuit comprising the variable voltage source (420b) comprises a first transistor (422b) and a second transistor (423b) connected to each other in a current mirror configuration, a variable current source (421b) connected between a first terminal (drain terminal of the transistor 422b) of the first transistor (422b) and a ground (ground) and configured to generate the variable current, and a first resistor (424b) connected between a first terminal (drain terminal of the transistor 423b) of the second transistor (423b) and the ground (ground). It would have been obvious to substitute Ohta et al’s variable voltage source (420b in Fig. 2 of Ohta et al) in place of Andrys et al’s variable voltage source (520 in Fig. 5 of Andrys et al) since Andrys et al discloses a generic variable voltage source thereby suggesting that any equivalent variable voltage source would have been usable in Andrys et al’s reference.
Regarding claim 12, wherein the limit current source (404) is connected to an output terminal (output terminal of 530) of the amplifier (530), and a voltage of the output terminal (output terminal of 530) of the amplifier (530) is a second voltage (output voltage of 530) that varies in response to the variable current (the current source in 520).
Regarding claim 13, wherein the limit current source (404) comprises a first transistor (512) comprising a control terminal (gate terminal of 512) to which the second voltage (output voltage of 530) is applied, a first terminal (drain terminal of the transistor 512) connected to the second input terminal (+ input terminal of 530) of the amplifier (530), a first resistor (513) connected between the first terminal (drain terminal of the transistor 512) of the first transistor (512) and a ground (ground), and a second transistor (511a) comprising a control terminal (gate terminal of the transistor 511a) to which the second voltage (output voltage signal of 530) is applied and a first terminal (drain terminal of the transistor 511a) which outputs the limit current (Ib_clamp).
Regarding claim 15, wherein the limit current (Ib_clamp) varies in response to the first voltage (output voltage signal of 520) and the second voltage (output voltage of 530).
Allowable Subject Matter
Claims 6, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (703)774-4614. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HENRY CHOE/ Primary Examiner, Art Unit 2843
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