DETAILED ACTION
Response to Amendments and Arguments
Applicant's amendments and arguments filed on 10/13/2025 have been fully considered but they are not persuasive.
The Applicant submitted that Ueno does not disclose or suggest “a clamp circuit, coupled to the gain stage and the output stage, to clamp the second output signal to have an upper limit lower than a power supply voltage of the comparator.” (Emphasis highlighted). The Applicant further explains that Ueno teaches in [0286]: “the clamp circuit 530 performs clamp processing such that the potential of the output node ND512 (A) of the first amplifier 510 does not become lower than the threshold voltage Vthn of the NMOS transistor NT512 forming a differential-pair transistor whose drain is connected to the output node ND512.” [0288]: “Thus, the clamp circuit 530 prevents the potential of the output node ND512 (A) from being lower than the constant potential and clamps the potentials of the nodes ND512 (A) and ND512 (B).” The Applicant asserts that Ueno serves to provide a lower limit for the node ND512, rather than an upper limit, and therefore Ueno fails to teach any clamp circuit or transistor capable of providing an upper limit lower than the power supply voltage of the comparator (Applicant’s remarks, pages 7-8).
In response, the Examiner understands the Applicant’s arguments and invention but respectfully disagrees with the Applicant’s assessment of the claimed limitations and interpretation of Ueno’s disclosure as set forth below:
The claim limitations are given their broadest reasonable interpretation. In this case, “an upper limit” recited in claim 1 can be interpreted as any limit that is higher than Vthn (above ground level) and does not exceed VDD in the conditions disclosed by Ueno because the amended claims 1 and 14 do not specifically distinguish between a lower limit (not in claims) and an upper limit, and do not require a specific timing for the upper limit that is lower than the power supply voltage of the comparator. From that perspective, the claimed limitations read on the disclosure in Ueno with respect to the clamp circuit 530 illustrated in Fig. 17 and paragraphs [0286]-[0288] in a broad condition as following: For example, in a condition where the output voltage at node ND512(A) drops to a level that is significantly below VDD and at potential Vthn of the transistor NT531, “the clamp circuit 530 performs clamp processing such that the potential of the output node ND512 (A) of the first amplifier 510 does not become lower than the threshold voltage Vthn of the NMOS transistor NT512 forming a differential-pair transistor whose drain is connected to the output node ND512… In other words, the clamp circuit 530 clamps the potential of the output node ND512 (A) such that the differential-pair transistor NT512 (M2) satisfies and maintains its saturated operation condition… Thus, the clamp circuit 530 prevents the potential of the output node ND512 (A) from being lower than the constant potential and clamps the potentials of the nodes ND512 (A) and ND512 (B).” Because the clamp circuit 530 maintains the voltage level of the output node ND512(A) above the threshold voltage Vthn in the case of voltage drop which is inherently way below VDD, the voltage level of the output node ND512(A) being clamped at this time must be lower than a power supply voltage of the comparator (VDD in Ueno) in such a clamping condition defined by threshold voltage Vthn. Secondly, as seen in Ueno, Vthn is higher than ground potential level and that is reasonable to interpret this limit as an upper limit (as the instant claims do not define a range for the upper limit discussed above). In other words, the teaching of Ueno encompasses the instant claimed limitations in a broad sense.
At least in view of the above, the claimed limitations are met by the disclosure of Ueno, and therefore the rejections of claims 1-12, 14-25 and 27 are maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-10, 11, 12, 14-17, 19-23, 25 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ueno (US 2013/0215302 A1).
Regarding claim 14, Ueno discloses an image sensing circuit (Figs. 9, 10 & 17), having a plurality of input channels, the image sensing circuit comprising:
a ramp generator (360) to generate a ramp signal (Figs. 9 & 10); and
a plurality of comparators (comparators 500 shown in Fig. 17 which is one version of comparators 351 in Fig. 10; see par. [0245]), each comprising:
an input stage (indicated by input terminals at TVSEL and TRAMP in Fig. 17), coupled to the ramp generator and one of the plurality of input channels, to receive an input signal from the coupled input channel and receive the ramp signal from the ramp generator (Fig. 17, par. [0256]-[0257]), and generate a first output signal (at ND512 in Fig. 17 and par. [0259], [0264]);
a gain stage (either first amplifier 510 or second amplifier 520, or both), coupled to the input stage, to receive the first output signal and generate a second output signal (Fig. 17 and par. [0245], [0250], [0264]-[0265]);
an output stage (at ND521 and TOUT), coupled to the gain stage, to receive the second output signal and generate a third output signal (par. [0274]); and
a clamp circuit (530), coupled to the gain stage and the output stage, to clamp the second output signal to have an upper limit lower than a power supply voltage of the comparator (see Fig. 17 and par. [0275], [0282]-[0289]. Please note the Examiner’s response in section 1 above for detailed explaination).
Regarding claim 15, Ueno also discloses that the gain stage comprises a high-side transistor (PT521) and a low-side transistor (NT521), and the clamp circuit comprises: a first clamp transistor (NT531), coupled between the high-side transistor and a power supply terminal (VDD) of the comparator (see Fig. 17 and par. [0276]).
Regarding claim 17, as further disclosed by Ueno, the first clamp transistor is a P-type metal oxide semiconductor (PMOS) transistor (see par. [0236]-[0241], wherein the first clamp transistor may be implemented by either NMOS or PMOS transistor).
Regarding claim 16, in case of PMOS as discussed in claim 17, it is also seen in Ueno that a drain terminal of the first clamp transistor is coupled to the high-side transistor, a source terminal of the first clamp transistor is coupled to the power supply terminal, and a gate terminal of the first clamp transistor is coupled to an output terminal of the gain stage (see Figs. 16A, 16B & 17 and par. [0236]-[0241] and note that when the first clamp transistor is implemented as PMOS, the above claimed limitations are met).
Regarding claim 19, Ueno further discloses that the first clamp transistor clamps the second output signal to have an upper limit (above Vthn, see par. [0286]-[0289]).
Regarding claim 20, as also seen in Ueno, the clamp circuit comprises: a second clamp transistor (NT531 – see further explanation), coupled between the gain stage and the output stage (see Fig. 17 and par. [0276]. It should be noted that the second transistor in this claim is considered as same as the first transistor NT531 in claim 15 since claims 15 and 20 are on separate dependent claim branches and this claim 20 does not require the second transistor to be different from the first transistor. Therefore, the broadest reasonable interpretation (BRI) is applied).
Regarding claim 21, Ueno further discloses a first terminal of the second clamp transistor is coupled to an output terminal of the gain stage (at ND512), a second terminal of the second clamp transistor is coupled to a power supply (VDD) terminal of the comparator, and a gate terminal of the second clamp transistor is coupled to the output stage (at ND521 and TOUT; see Fig. 17 and par. [0276]).
Regarding claim 22, Ueno further discloses that the second clamp transistor is a PMOS transistor (see par. [0236]-[0241] and also note the discussion in claim 20 for the interpretation of the second clamp transistor).
Regarding claim 23, as disclosed by Ueno, the second clamp transistor (NT531) is an N-type metal oxide semiconductor (NMOS) transistor (see Fig. 17 and par. [0275]-[0276]).
Regarding claim 25, Ueno further discloses that the second clamp transistor clamps the second output signal to have a lower limit higher than a ground voltage (see par. [0286]-[0289]).
Regarding claim 27, Ueno also discloses that the image sensing circuit further comprises a plurality of counters (352 shown in Figs. 10 & 12), each coupled to an output terminal of one of the plurality of comparators (see Figs. 10 & 12).
Regarding claims 1-4, 6-10 and 12, the limitations of these claims are also met by the discussions in claims 14-17, 19-23 and 25, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 11, 18 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Ueno in view of Tomita et al. (US 2023/0412942 A1).
Regarding claim 5, although Ueno is silent about the clamp circuit comprising a first enable switch coupled between the first clamp transistor and the power supply terminal, such lack of teaching is compensated by Tomita in Fig. 6, clamp circuit 360 in which an enable transistor (361) coupled between a clamp transistor (362) and a power supply terminal (VDDHSN) so as to effectively control the clamp operation by the control signal CLPEN from a control circuit (see Tomita, par. [0093]-[0094]).
Therefore, it would have been obvious to one of ordinary skill in the art to provide an enable switch as taught by Tomita to arrive at the claimed invention to effectively start and stop the clamp operation for better image quality control.
Regarding claim 11, please refer to the discussion in claim 5 for similar limitations. Also note claims 7 & 20 regarding the second claim transistor.
Regarding claims 18 and 24, refer to the discussions in claims 5 and 11 above.
Allowable Subject Matter
Claims 13 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 13 and 26, the prior art references of record fail to teach or suggest: “the gain stage comprises a high-side transistor and a low-side transistor, and the low-side transistor keeps on when the second output signal is at a high level and when the second output signal is at a low level.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NHAN T TRAN/Primary Examiner, Art Unit 2638