DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-5, 7-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Thottethodi et al. (Pub. No. US20140177626)
As per claim 1, Thottethodi discloses an integrated circuit (fig.1, 100) comprising:
a core region of logic circuits (fig.1, core processing logic in dice 104-107); and
a peripheral region (fig.1, 124) comprising a first conductor (fig.1, 116) coupled to transmit a first signal (paragraph 26, lines 5-6, information is formatted as a packet to be transmitted to from the CPU on die 105 to the memory controller on die 107) between first (fig.2, 204) and second (fig.2, 206) devices that are external to the integrated circuit, wherein the first and the second devices are oriented diagonally (see figure 2) in a multi-chip module (fig.1, 102).
As per claim 2, Thottethodi discloses wherein the peripheral region further comprises a time division multiplexer circuit (fig.4, a crossbar switch 402 in logic 124) coupled to provide a second signal (paragraph 26, lines 5-6, information is formatted as a packet) to the first device.
As per claim 3, Thottethodi discloses wherein the peripheral region further comprises a time division multiplexer circuit (fig.4, a crossbar switch 402 in logic 124) coupled to receive a second signal (paragraph 26, lines 5-6, information is formatted as a packet) from the second device (fig.2, 206).
As per claim 4, Thottethodi discloses wherein the first conductor is coupled to transmit the first signal (paragraph 26, lines 5-6, information is formatted as a packet) entirely through the peripheral region without routing the first signal through the core region (paragraph 27, logic on die 104 then issues the packet by manipulating the physical interface (PHY) connected to the conductors that comprise link 119 connected to die 107 to transmit signaling representative of the memory write request.)
As per claim 5, Thottethodi discloses wherein the peripheral region further comprises: a second conductor (fig.2, logic 124) coupled to transmit a second signal (paragraph 26, lines 5-6, information is formatted as a packet) between the second device and a third device (fig.2, 215) that is external to the integrated circuit.
As per claim 7, Thottethodi discloses a circuit system comprising: a support device (fig.1, 102) comprising first (fig.1, 116) and second conductors (fig.2, logic 124); and
first, second, and third integrated circuits (fig.1, 104-107)that are coupled to the support device, wherein the second integrated circuit comprises a first peripheral region(fig.1, 124), wherein the first peripheral region comprises a third conductor (fig.1, 119) coupled between the first and the second conductors (see figures 1 and 2), wherein the circuit system is configured to transmit a first signal (paragraph 26, lines 5-6, information is formatted as a packet) from the first integrated circuit through the first conductor(fig.1, 116), the third conductor(fig.1, 119), and the second conductor (fig.2, logic 124) to the third integrated circuit, and wherein the first and the third integrated circuits are positioned diagonally (see figure 2) in the circuit system (paragraph 22, each of the horizontally stacked die 104-107 includes corresponding routing logic (identified as routing logic 124, 125, 126, and 127, respectively)).
As per claim 8, Thottethodi discloses wherein the support device comprises a first interconnection bridge (fig.1, 116 in interposer 102) that comprises the first conductor and a second interconnection bridge (fig.1, 119 in interposer 102) that comprises the second conductor (fig.2, logic 124).
As per claim 9, Thottethodi discloses wherein the second integrated circuit further comprises a core region of logic circuits, and wherein the third conductor is coupled to transmit the first signal entirely through the first peripheral region without routing the first signal through the core region (paragraph 27, logic on die 104 then issues the packet by manipulating the physical interface (PHY) connected to the conductors that comprise link 119 connected to die 107 to transmit signaling representative of the memory write request.)
As per claim 10, Thottethodi discloses wherein the first peripheral region of the second integrated circuit further comprises a first time division multiplexer circuit (fig. 1, multiplexer 402 in logic 124) coupled to transmit a second signal (paragraph 26, lines 5-6, information is formatted as a packet) through a fourth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127) in the support device to the third integrated circuit.
As per claim 11, Thottethodi discloses wherein the third integrated circuit comprises a second peripheral region (fig.1, 127), and wherein the second peripheral region (fig.1, 127) comprises a fifth conductor coupled between the fourth conductor and a sixth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127) in the support device.
As per claim 12, Thottethodi discloses the circuit system further comprising: a fourth integrated circuit (fig.1, 106) comprising a second time division multiplexer circuit(fig.1, 402 in routing logic 127), wherein the circuit system is configured to transmit the second signal from the first time division multiplexer circuit (fig.1, 402 in routing logic 125) through the fourth conductor, the fifth conductor, and the sixth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127) to the second time division multiplexer circuit(fig.1, 402 in routing logic 127).
As per claim 13, Thottethodi discloses the circuit system further comprising: a fourth integrated circuit comprising a second peripheral region (fig.1, second peripheral region 126), wherein the support device further comprises a fourth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127)coupled between the third (fig.1, 107) and the fourth integrated circuits, wherein the support device further comprises a fifth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127) coupled between the first and the fourth integrated circuits, and wherein the second peripheral region comprises a sixth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127) coupled between the fourth and the fifth conductors(fig.1, 105).
As per claim 14, Thottethodi discloses wherein the circuit system is configured to transmit a second signal from the third integrated circuit through the fourth conductor, the fifth conductor, and the sixth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127) to the first integrated circuit.
As per claim 15, Thottethodi discloses the circuit system further comprising: a fourth integrated circuit (fig.1, one of 111-113) that is vertically stacked on, and coupled to, the first integrated circuit(fig.1, 105); and a fifth integrated circuit that is vertically stacked on (paragraph 24, lines 2-3, outing logic 127 is implemented on the die 107 disposed adjacent to the interposer 102 for the vertical die stack 110), and coupled to, the third integrated circuit(fig.1, 107).
As per claim 16, Thottethodi discloses a method comprising:
transmitting a first signal (paragraph 26, lines 5-6, information is formatted as a packet to be transmitted) from a first time division multiplexer circuit (routing logic 125) in a first integrated circuit (fig.1, 105) through a first conductor (fig.1, 116) in a support device (fig.1, 102) to a second integrated circuit (fig.1, 104);
transmitting the first signal from the first conductor (fig.1, 116) through a second conductor (fig.2, logic 124) that is routed through a first peripheral region (fig.1, 124) of the second integrated circuit (fig.1, 104) to a third conductor (fig.1, 119) in the support device (fig.1, 102); and
transmitting the first signal from the third conductor to a second time division multiplexer circuit (fig.1, routing logic 127) in a third integrated circuit (fig.1, 107).
As per claim 17, Thottethodi discloses the method further comprising: transmitting a second signal (paragraph 26, lines 5-6, information is formatted as a packet) from a third time division multiplexer circuit (fig.1, 119) in the second integrated circuit (fig.1, 104) through a fourth conductor (fig.1, conductors at the multiplexers 402 of 124 and 127) in the support device to the first integrated circuit(fig.1, 105); transmitting the second signal (paragraph 26, lines 5-6, information is formatted as a packet) from the fourth conductor through a fifth conductor that is routed through a second peripheral region of the first integrated circuit to a sixth conductor in the support device(fig.1, conductors at the multiplexers 402 of 124 and 127); and transmitting the second signal from the sixth conductor to a fourth time division multiplexer circuit(fig.1, conductors at the multiplexers 402 of 124 and 127) in a fourth integrated circuit.
As per claim 18, Thottethodi discloses wherein the second integrated circuit (fig.1, 104); further comprises a core region(fig.1, core processing logic in dice 104-107), and wherein the second conductor is coupled to transmit the first signal entirely through the first peripheral region without routing the first signal through the core region(paragraph 27, logic on die 104 then issues the packet by manipulating the physical interface (PHY) connected to the conductors that comprise link 119 connected to die 107 to transmit signaling representative of the memory write request.)
As per claim 19, Thottethodi discloses the method further comprising: generating the first signal from second signals (paragraph 26, lines 5-6, information is formatted as a packet) received from a first core region (fig.1, core processing logic in dice 104-107) of the first integrated circuit using the first time division multiplexer circuit(fig.1, 402 in routing logic 125); generating third signals (paragraph 26, lines 5-6, information is formatted as a packet) from the first signal using the second time division multiplexer circuit(fig.1, 402 in routing logic 127); and transmitting the third signals to a second core region (fig.1, core processing logic in dice 104-107) of the third integrated circuit(paragraph 26, lines 5-6, information is formatted as a packet).
As per claim 20, Thottethodi discloses wherein the first, the second, and the third integrated circuits (fig.1, 104-107) are mounted on the support device (fig.1, 102), and wherein the first and the third integrated circuits are positioned diagonally in the circuit system (paragraph 13, an electronic assembly includes horizontally-stacked die disposed at an interposer.)
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Thottethodi et al. (Pub. No. US20140177626) in view of Hesselbom et al. (US Patent No. US5963689)
Thottethodi discloses all the limitations as the above but does not explicitly discloses wherein the second device is adjacent to a second edge of the integrated circuit that is perpendicular to the first edge. However, Hesselbom discloses this. (col.3, lines 52-55, the three-dimensional multi-chip modules are all located on top of each other to have lateral side or edge surfaces 3 located in substantially the same plane perpendicular to the large surfaces of the substrates.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Hesselbom with the teaching of Thottethodi to provide structural strength, stable alignment so as to yield the predicatable result to control efficiently, thus enhance the system performance.
5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Pyeon [Pub. No. US20130141858] discloses a multi-chip package has a substrate with electrical contacts for connection to an external device.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights