DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed February 5, 2026 has been entered. Claims 1-4, 6-18, and 20 remain pending in the application. Applicant’s amendments to the specification and claims have overcome each and every objection previously presented in the Non-Final Office Action mailed December 19, 2025, with one exception outlined below.
The objection to the specification based on improper trademarks remains because the instant specification was not amended to comply with the objection, and no arguments were presented by the applicant that the objection is inappropriate.
Response to Arguments
Applicant’s arguments, see pages 8-12, filed February 5, 2026, with respect to the rejections of claims 1-4, 6-18, and 20 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference Xu et al. (Patent Number CN 209,072,437 U), hereafter referred to as Xu.
Specification
The use of the terms “Wi-Fi®”, “WiMax®”, and “BLUETOOTH®” (see Paragraph 47), which are trade names or marks used in commerce, has been noted in this application. The terms should be accompanied by the generic terminology; furthermore the terms should be capitalized wherever they appear or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the terms.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Takenaka (Patent Publication Number US 2025/0088161 A1), hereafter referred to as Takenaka, in view of Xu.
Regarding claim 1, Takenaka discloses:
A power amplifier (Takenaka, Fig. 1, 10) configured to amplify an input radio-frequency (RF) signal (Fig. 1, 101), the power amplifier comprising: a first power transistor (Fig. 1, 11, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 11); a bias circuit (Fig. 1, 104) configured to supply a bias current to the input terminal of the first power transistor (Paragraph 50, lines 7-10); but fails to disclose a first capacitor having a first end connected to the input terminal of the first power transistor; and a resistor having a first end connected to a second end of the first capacitor and a second end connected to a ground, wherein the input RF signal is input to the second end of the first capacitor and the first end of the resistor, and wherein the first capacitor is disposed between the bias circuit and the resistor, and is configured to block the bias current supplied from the bias circuit from leaking to the ground through the resistor.
However, Xu teaches a first capacitor (Xu, Fig. 5, C3) having a first end connected to the input terminal of the first power transistor (Fig. 5, see connection between C3 and M13); and a resistor (Fig. 5, R2) having a first end connected to a second end of the first capacitor (Fig. 5, see connection between C3 and R2) and a second end connected to a ground (Fig. 5, see connection between R2 and ground), wherein the input RF signal is input to the second end of the first capacitor and the first end of the resistor (Fig. 5, see connection between RF_IN, C3, and R2), and wherein the first capacitor is disposed between the bias circuit and the resistor (Fig. 5, see connection between R2 and bias circuit DRIVE_BIAS via capacitor C3), and is configured to block the bias current supplied from the bias circuit from leaking to the ground through the resistor (Page 4, Paragraph 5, lines 1-7).
Takenaka and Xu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Xu to include the RC network of Xu in the circuit of Takenaka, which would have the effect of reducing power consumption (Xu, Page 5, Paragraph 7, lines 1-5).
Regarding claim 9, Takenaka discloses:
A power amplifier, (Takenaka, Fig. 1, 10) comprising: a first power transistor (Fig. 1, 11, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 11); a second power transistor (Fig. 1, 12, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 12); but fails to disclose a first capacitor having a first end connected to the input terminal of the first power transistor; a first resistor having a first end connected to a second end of the first capacitor and a second end connected to a ground; a second capacitor having a first end connected to the input terminal of the second power transistor; and a second resistor having a first end connected to a second end of the second capacitor and a second end directly connected to the ground.
However, Xu teaches a first capacitor (Xu, Fig. 5, C3) having a first end connected to the input terminal of the first power transistor (Fig. 5, see connection between C3 and M13); a first resistor (Fig. 5, R2) having a first end connected to a second end of the first capacitor (Fig. 5, see connection between R2 and C3) and a second end connected to a ground (Fig. 5, see connection between R2 and ground); a second capacitor (Fig. 5, C1) having a first end connected to the input terminal of the second power transistor (Fig. 5, see connection between C1 and M1); and a second resistor (Fig. 5, R1) having a first end connected to a second end of the second capacitor (Fig. 5, see connection between R1 and C1) and a second end directly connected to the ground (Fig. 5, see connection between R1 and ground).
Takenaka and Xu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Xu to include the RC network of Xu in the circuit of Takenaka, which would have the effect of reducing power consumption (Xu, Page 5, Paragraph 7, lines 1-5).
Regarding claim 14, Takenaka further discloses:
further comprising an output transformer (Takenaka, Fig. 1, 21) configured to combine an output signal of the first power transistor with an output signal of the second power transistor (Paragraph 57, lines 11-15).
Regarding claim 15, Takenaka discloses:
A power amplifier (Takenaka, Fig. 1, 10) comprising: a first power transistor (Fig. 1, 11, see also Paragraph 52, lines 1-10) configured to amplify an input radio-frequency (RF) signal to produce a first amplified output RF signal (Paragraph 51, lines 1-9) and comprising a first input terminal configured to receive the input RF signal (Fig. 1, see input of 11), and a first output terminal configured to output the first amplified output RF signal (Fig. 1, see connection between output of 11 and 102); a bias circuit (Fig. 1, 104) configured to supply a bias current to the first input terminal of the first power transistor (Paragraph 50, lines 7-10); but fails to disclose a first element having an impedance value that decreases as frequency increases and having a first end connected to the first input terminal of the first power transistor; and a second element having an impedance value that is substantially independent of frequency and having a first end connected to a second end of the first element and a second end connected to a ground, wherein the first element is disposed between the bias circuit and the second element and is configured to block the bias current supplied from the bias circuit from leaking to the ground through the second element.
However, Xu teaches a first element (Xu, Fig. 5, C3) having an impedance value that decreases as frequency increases (Fig. 5, consider that C3 is a capacitor) and having a first end connected to the first input terminal of the first power transistor (Fig. 5, see connection between C3 and M13); and a second element (Fig. 5, R2) having an impedance value that is substantially independent of frequency (Fig. 5, consider that R2 is a resistor) and having a first end connected to a second end of the first element (Fig. 5, see connection between R2 and C3) and a second end connected to a ground (Fig. 5, see connection between R2 and ground), wherein the first element is disposed between the bias circuit and the second element (Fig. 5, see connection between R2 and bias circuit DRIVE_BIAS via capacitor C3) and is configured to block the bias current supplied from the bias circuit from leaking to the ground through the second element (Page 4, Paragraph 5, lines 1-7).
Takenaka and Xu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Xu to include the RC network of Xu in the circuit of Takenaka, which would have the effect of reducing power consumption (Xu, Page 5, Paragraph 7, lines 1-5).
Regarding claim 20, Takenaka further discloses:
further comprising: a second power transistor configured to amplify the input RF signal to produce a second amplified output RF signal (Takenaka, Fig. 1, 12, see also Paragraph 52, lines 1-10) and comprising a second input terminal configured to receive the input RF signal (Fig. 1, see input of 12), and a second output terminal configured to output the second amplified output RF signal and connected to the first output terminal of the first power transistor (Fig. 1, see connection between output of 12 and 102); but fails to disclose and a third element having an impedance value that decreases as frequency increases and having a first end connected to the second input terminal of the second power transistor, and a second end connected to the second end of the first element and the first end of the second element.
However, Xu further teaches and a third element (Xu, Fig. 5, C1) having an impedance value that decreases as frequency increases (Fig. 5, consider that C1 is a capacitor) and having a first end connected to the second input terminal of the second power transistor (Fig. 5, see connection between C1 and M1), and a second end connected to the second end of the first element and the first end of the second element (Fig. 5, see connection between C1, C3, and R2).
Takenaka and Xu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Xu to include the RC network of Xu in the circuit of Takenaka, which would have the effect of reducing power consumption (Xu, Page 5, Paragraph 7, lines 1-5).
Claims 2-4, 6-8, 10-13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Takenaka in view of Xu as applied to claim 1 (for claims 2-4 and 6-8), claim 9 (for claims 10-13), or claim 15 (for claims 16-17) above, and further in view of Shen et al. (Patent Number CN 203,786,508 U), hereafter referred to as Shen.
Regarding claim 2, Takenaka fails to disclose:
wherein a low-frequency signal comprising a noise included in the input RF signal is bypassed to the ground through the resistor.
However, Shen further teaches wherein a low-frequency signal comprising a noise included in the input RF signal is bypassed to the ground through the resistor (Shen, Paragraph 21, lines 25-28).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 3, Takenaka fails to disclose:
wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal.
However, Shen further teaches wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal (Shen, Paragraph 21, lines 25-28).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 4, Takenaka fails to disclose:
wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor.
However, Shen further teaches wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor (Shen, Fig. 2, see path from MIC1 to MICN via C15).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 6, Takenaka further discloses:
further comprising: a second power transistor (Takenaka, Fig. 1, 12, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 12) and an output terminal connected to an output terminal of the first power transistor (Fig. 1, see connection between output of 12 and 102); but fails to disclose and a second capacitor connected between the first end of the resistor and the input terminal of the second power transistor.
However, Shen further teaches and a second capacitor (Shen, Fig. 2, C14) connected between the first end of the resistor and the input terminal of the second power transistor (Fig. 2, see connection between MICP and R8 via C14 and MIC1).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 7, Takenaka fails to disclose:
wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor, and passes through the second capacitor to be input to the input terminal of the second power transistor.
However, Shen further teaches wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor (Shen, Fig. 2, see connection between MIC1 and MICN via C15), and passes through the second capacitor to be input to the input terminal of the second power transistor (Fig. 2, see connection between MIC1 and MICP via C14).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 8, Takenaka further discloses:
further comprising: a first bias circuit (Takenaka, Fig. 1, 104) configured to supply a first bias current to the input terminal of the first power transistor (Paragraph 50, lines 7-10); and a second bias circuit (Fig. 1, 104) configured to supply a second bias current to the input terminal of the second power transistor (Paragraph 50, lines 7-10).
Regarding claim 10, Takenaka further discloses:
further comprising an input transformer (Takenaka, Fig. 1, 22) configured to convert an input radio-frequency (RF) signal to a first differential signal and a second differential signal (Paragraph 55, lines 11-15), but fails to disclose wherein the first differential signal is input to the second end of the first capacitor and the first end of the first resistor, and the second differential signal is input to the second end of the second capacitor and the first end of the second resistor.
However, Shen further teaches wherein the first differential signal is input to the second end of the first capacitor and the first end of the first resistor (Shen, Fig. 2, see connection between MIC-, R8, and C15), and the second differential signal is input to the second end of the second capacitor and the first end of the second resistor (Fig. 2, see connection between MIC+, C14, and R6).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 11, Takenaka fails to disclose:
wherein a low-frequency signal comprising a noise included in the first differential signal is bypassed to the ground through the first resistor, and a low-frequency signal comprising a noise included in the second differential signal is bypassed to the ground through the second resistor.
However, Shen further teaches wherein a low-frequency signal comprising a noise included in the first differential signal is bypassed to the ground through the first resistor (Shen, Paragraph 21, lines 25-28), and a low-frequency signal comprising a noise included in the second differential signal is bypassed to the ground through the second resistor (Paragraph 21, lines 25-28, see also Fig. 2, connection between R6 and ground via C10).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 12, Takenaka fails to disclose:
wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal.
However, Shen further teaches wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal (Shen, Paragraph 21, lines 25-28).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 13, Takenaka fails to disclose:
wherein the first differential signal passes through the first capacitor to be input to the input terminal of the first power transistor, and the second differential signal passes through the second capacitor to be input to the input terminal of the second power transistor.
However, Shen further teaches wherein the first differential signal passes through the first capacitor to be input to the input terminal of the first power transistor (Shen, Fig. 2, see connection between MIC1 and MICN via C15), and the second differential signal passes through the second capacitor to be input to the input terminal of the second power transistor (Fig. 2, see connection between MIC1 and MICP via C14).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 16, Takenaka fails to disclose:
wherein a low-frequency signal included in the input RF signal is bypassed to the ground through the second element.
However, Shen further teaches wherein a low-frequency signal included in the input RF signal is bypassed to the ground through the second element (Shen, Paragraph 21, lines 25-28).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 17, Takenaka fails to disclose:
wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal.
However, Shen further teaches wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal (Shen, Paragraph 21, lines 25-28).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 18, Takenaka fails to disclose:
wherein the input RF signal passes through the first element to be input to the first input terminal of the first power transistor.
However, Shen further teaches wherein the input RF signal passes through the first element to be input to the first input terminal of the first power transistor (Shen, Fig. 2, see path from MIC1 to MICN via C15).
Takenaka, Xu, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (Patent Publication Number CN 107,861,899 A) discloses (Fig. 2) an RC network for removing low-frequency noise.
Sugiyama et al. (Patent Number JP 5,488,955 B2) discloses (Fig. 5) an input RC network for removing low-frequency noise.
Gunaa (Patent Number JP S60,233,920 A) discloses (Fig. 1) an amplifier with two parallel paths having resistors that couple amplifier inputs to ground.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843