DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed August 17, 2026, has been entered. Claims 1-4, 6-9, 11-18, and 20 remain pending in the application. Applicant’s amendments to the claims have overcome each and every 35 U.S.C. § 112 rejection previously presented in the Non-Final Office Action mailed June 3, 2026.
Response to Arguments
Applicant's arguments filed August 17, 2026, have been fully considered but they are not persuasive. Applicant argues, see pages 8-13, that previously presented prior art reference Phelps et al. (Patent Publication Number US 2016/0065136 A1), hereafter referred to as Phelps, fails to disclose a resistor continuously connected in a shunt configuration between the signal input node and the ground to bypass a low-frequency signal, and that therefore the combination of previously presented prior art reference Takenaka (Patent Publication Number US 2025/0088161 A1), hereafter referred to as Takenaka, and Phelps relies on impermissible hindsight reasoning, lacks a sufficient motivation to combine, and would destroy the original intent of Takenaka. Applicant further argues that previously presented prior art reference Shen et al. (Patent Number CN 203,786,508 U), hereafter referred to as Shen, is not analogous to the instant application, and that therefore the combination of Takenaka, Phelps, and Shen is nonobvious. Examiner respectfully disagrees.
Regarding applicant’s first argument, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a resistor continuously connected in a shunt configuration between the signal input node and the ground to bypass a low-frequency signal) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In this case, the independent claims merely require the resistor connected in a shunt configuration between the signal input node and the ground, and do not specify a continuous and/or direct connection between the resistor and the signal input node. This broader feature is fully disclosed by Phelps, as the termination resistor of Phelps is connected between the signal input node (via a switch) and ground, and is designed to provide a low impedance path to ground when activated by the switch, resulting in a shunt configuration. Additionally, only the dependent claims recite a resistor connected to bypass a low-frequency signal, a feature fully disclosed by Shen.
Therefore, the combination of Takenaka and Phelps does disclose the invention as claimed by the independent claims. Furthermore, in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In this case, all the claimed features are disclosed in Takenaka and Phelps, and including the termination resistor of Phelps in the circuit of Takenaka would have the benefit of reducing power consumption (Phelps, Paragraph 43, lines 11-15). For the same reason, the combination of Takenaka and Phelps does have sufficient motivation to combine, namely, to reduce power consumption of the circuit of Takenaka.
Furthermore, as the combination of Takenaka and Phelps does not require continuously connecting the termination resistor of Phelps in the circuit of Takenaka, the combination would not destroy the original intent of Takenaka.
Regarding applicant’s second argument, in response to applicant's argument that Shen is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992).
In this case, while Shen is not an RF power amplifier, it is an audio amplifier, which will be pertinent to an RF power amplifier in some aspects. Namely, both RF power amplifiers and audio amplifiers will experience undesirable noise effects, which one of ordinary skill in the art of amplifiers would want to correct by incorporating a low-frequency noise cancelling resistor, as taught by Shen, in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Therefore, all of applicant’s arguments are unconvincing, and the rejections of claims 1-4, 6-9, 11-18, and 20 are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Takenaka in view of Phelps.
Regarding claim 1, Takenaka discloses:
A power amplifier (Takenaka, Fig. 1, 10) configured to amplify an input radio-frequency (RF) signal (Fig. 1, 101), the power amplifier comprising: a first power transistor (Fig. 1, 11, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 11); a bias circuit (Fig. 1, 104) configured to supply a bias current to the input terminal of the first power transistor (Paragraph 50, lines 7-10); but fails to disclose a first capacitor having a first end connected to the input terminal of the first power transistor; and a resistor having a first end connected to a second end of the first capacitor and a second end connected to a ground, wherein the input RF signal is input to the second end of the first capacitor and the first end of the resistor, wherein the first capacitor is connected in series between the input terminal of the first power transistor and a signal input node to which the input RF signal is supplied, and the resistor is connected in a shunt configuration between the signal input node and the ground, and wherein the first capacitor is disposed on a direct current (DC) path between the input terminal and the resistor, and the first capacitor is configured to block the bias current supplied from the bias current at the input terminal from leaking to the ground through the resistor.
However, Phelps teaches a first capacitor (Phelps, Fig. 8, 48) having a first end connected to the input terminal of the first power transistor (Fig. 8, see connection between 48 and 44); and a resistor (Fig. 8, 47) having a first end connected to a second end of the first capacitor (Fig. 8, see connection between 48 and 47) and a second end connected to a ground (Fig. 8, see connection between 47 and ground), wherein the input RF signal is input to the second end of the first capacitor and the first end of the resistor (Fig. 8, see connection between input signal arrow, and capacitor 48 and resistor 47), wherein the first capacitor is connected in series between the input terminal of the first power transistor and a signal input node to which the input RF signal is supplied (Fig. 8, see connection between input node and amplifier 44 via capacitor 48), and the resistor is connected in a shunt configuration between the signal input node and the ground (Fig. 8, see connection between input node and ground via resistor 47), and wherein the first capacitor is disposed on a direct current (DC) path between the input terminal and the resistor (Fig. 8, consider that capacitor 48 is labelled as a “DC Blocking Capacitor” and is located between the amplifier 44 and the resistor 47), and the first capacitor is configured to block the bias current supplied from the bias current at the input terminal from leaking to the ground through the resistor (Fig. 8, consider that capacitor 48 is labelled as a “DC Blocking Capacitor” and is located between the amplifier 44 and the resistor 47).
Takenaka and Phelps are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Phelps to include the RC network of Phelps in the circuit of Takenaka, which would have the effect of reducing power consumption (Phelps, Paragraph 43, lines 11-15).
Regarding claim 9, Takenaka discloses:
A power amplifier, (Takenaka, Fig. 1, 10) comprising: a first power transistor (Fig. 1, 11, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 11); a second power transistor (Fig. 1, 12, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 12); an input transformer (Fig. 1, 22) configured to convert an input radio-frequency (RF) signal to a first differential signal and a second differential signal (Paragraph 55, lines 11-15); but fails to disclose a first capacitor having a first end connected to the input terminal of the first power transistor; a first resistor having a first end connected to a second end of the first capacitor and a second end connected to a ground; a second capacitor having a first end connected to the input terminal of the second power transistor; and a second resistor having a first end connected to a second end of the second capacitor and a second end directly connected to the ground, wherein the first differential signal is input to the second end of the first capacitor and the first end of the first resistor, and the second differential signal is input to the second end of the second capacitor and the first end of the second resistor, and wherein the first resistor and the second resistor are configured to bypass a common mode signal, which is included in the first and second differential signals due to an imbalance of the input transformer, to the ground to improve a stability factor and prevent oscillation of the power amplifier.
However, Phelps teaches a first capacitor (Phelps, Fig. 8, 48) having a first end connected to the input terminal of the first power transistor (Fig. 8, see connection between 48 and 44); a first resistor (Fig. 8, 47) having a first end connected to a second end of the first capacitor (Fig. 8, see connection between 48 and 47) and a second end connected to a ground (Fig. 8, see connection between 47 and ground); a second capacitor (Fig. 8, 48) having a first end connected to the input terminal of the second power transistor (Fig. 8, see connection between 48 and 44); and a second resistor (Fig. 8, 47) having a first end connected to a second end of the second capacitor (Fig. 8, see connection between 48 and 47) and a second end directly connected to the ground (Fig. 8, see connection between 47 and ground), wherein the first differential signal is input to the second end of the first capacitor and the first end of the first resistor (Fig. 8, see connection between input signal arrow, and capacitor 48 and resistor 47), and the second differential signal is input to the second end of the second capacitor and the first end of the second resistor (Fig. 8, see connection between input signal arrow, and capacitor 48 and resistor 47), and wherein the first resistor and the second resistor are configured to bypass a common mode signal, which is included in the first and second differential signals due to an imbalance of the input transformer, to the ground (Fig. 8, consider implementing the RC network of Phelps on both paths of the amplifier of Takenaka, which will result in the resistors of Phelps bypassing the common mode signal due to fundamental transformer imbalances present in the differential amplifier of Takenaka) to improve a stability factor and prevent oscillation of the power amplifier (Paragraph 10, lines 1-6, consider that reducing excess heat generation will improve reliability/stability of a circuit).
Takenaka and Phelps are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Phelps to include the RC network of Phelps in the circuit of Takenaka, which would have the effect of reducing power consumption (Phelps, Paragraph 43, lines 11-15).
Regarding claim 14, Takenaka further discloses:
further comprising an output transformer (Takenaka, Fig. 1, 21) configured to combine an output signal of the first power transistor with an output signal of the second power transistor (Paragraph 57, lines 11-15).
Regarding claim 15, Takenaka discloses:
A power amplifier (Takenaka, Fig. 1, 10) comprising: a first power transistor (Fig. 1, 11, see also Paragraph 52, lines 1-10) configured to amplify an input radio-frequency (RF) signal to produce a first amplified output RF signal (Paragraph 51, lines 1-9) and comprising a first input terminal configured to receive the input RF signal (Fig. 1, see input of 11), and a first output terminal configured to output the first amplified output RF signal (Fig. 1, see connection between output of 11 and 102); a bias circuit (Fig. 1, 104) configured to supply a bias current to the first input terminal of the first power transistor (Paragraph 50, lines 7-10); but fails to disclose a first element having an impedance value that decreases as frequency increases and having a first end connected to the first input terminal of the first power transistor; and a second element having an impedance value that is substantially independent of frequency and having a first end connected to a second end of the first element and a second end connected to a ground, wherein the first element is disposed between the bias circuit and the second element and is configured to block the bias current supplied from the bias circuit from leaking to the ground through the second element, wherein the first element is connected in series between the first input terminal of the first power transistor and a signal input node to which the input RF signal is supplied, and the second element is connected in a shunt configuration between the signal input node and the ground, and wherein the first element is disposed on a direct current (DC) path between the first input terminal and the second element, and the first element is configured to block the bias current supplied from the bias circuit at the first input terminal from leaking to the ground through the second element.
However, Phelps teaches a first element (Phelps, Fig. 8, 48) having an impedance value that decreases as frequency increases (Fig. 8, consider that 48 is a capacitor) and having a first end connected to the first input terminal of the first power transistor (Fig. 8, see connection between 48 and 44); and a second element (Fig. 8, 47) having an impedance value that is substantially independent of frequency (Fig. 8, consider that 47 is a resistor) and having a first end connected to a second end of the first element (Fig. 8, see connection between 48 and 47) and a second end connected to a ground (Fig. 8, see connection between 47 and ground), wherein the first element is disposed between the bias circuit and the second element (Fig. 8, consider that capacitor 48 is located between the amplifier 44 and the resistor 47, and that in Fig. 1 of Takenaka, the bias circuit is directly connected to the amplifier) and is configured to block the bias current supplied from the bias circuit from leaking to the ground through the second element (Fig. 8, consider that capacitor 48 is labelled as a “DC Blocking Capacitor” and is located between the amplifier 44 and the resistor 47), wherein the first element is connected in series between the first input terminal of the first power transistor and a signal input node to which the input RF signal is supplied (Fig. 8, see connection between input node and amplifier 44 via capacitor 48), and the second element is connected in a shunt configuration between the signal input node and the ground (Fig. 8, see connection between input node and ground via resistor 47), and wherein the first element is disposed on a direct current (DC) path between the first input terminal and the second element (Fig. 8, consider that capacitor 48 is labelled as a “DC Blocking Capacitor” and is located between the amplifier 44 and the resistor 47), and the first element is configured to block the bias current supplied from the bias circuit at the first input terminal from leaking to the ground through the second element (Fig. 8, consider that capacitor 48 is labelled as a “DC Blocking Capacitor” and is located between the amplifier 44 and the resistor 47).
Takenaka and Phelps are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Phelps to include the RC network of Phelps in the circuit of Takenaka, which would have the effect of reducing power consumption (Phelps, Paragraph 43, lines 11-15).
Regarding claim 20, Takenaka further discloses:
further comprising: a second power transistor configured to amplify the input RF signal to produce a second amplified output RF signal (Takenaka, Fig. 1, 12, see also Paragraph 52, lines 1-10) and comprising a second input terminal configured to receive the input RF signal (Fig. 1, see input of 12), and a second output terminal configured to output the second amplified output RF signal and connected to the first output terminal of the first power transistor (Fig. 1, see connection between output of 12 and 102); but fails to disclose and a third element having an impedance value that decreases as frequency increases and having a first end connected to the second input terminal of the second power transistor, and a second end connected to the second end of the first element and the first end of the second element.
However, Phelps further teaches and a third element (Phelps, Fig. 8, 48) having an impedance value that decreases as frequency increases (Fig. 8, consider that 48 is a capacitor) and having a first end connected to the second input terminal of the second power transistor (Fig. 8, see connection between 48 and 44), and a second end connected to the second end of the first element and the first end of the second element (Fig. 8, consider an implementation with the RC network of Phelps included in both paths of the differential amplifier of Takenaka, wherein the resistor 47 of Phelps is connected to one instance of capacitor 48 directly, and the other instance via the transformer of Takenaka).
Takenaka and Phelps are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Phelps to include the RC network of Phelps in the circuit of Takenaka, which would have the effect of reducing power consumption (Phelps, Paragraph 43, lines 11-15).
Claims 2-4, 6-8, 11-13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Takenaka in view of Phelps as applied to claim 1 (for claims 2-4 and 6-8), claim 9 (for claims 11-13), or claim 15 (for claims 16-18) above, and further in view of Shen.
Regarding claim 2, Takenaka fails to disclose:
wherein a low-frequency signal comprising a noise included in the input RF signal is bypassed to the ground through the resistor.
However, Shen further teaches wherein a low-frequency signal comprising a noise included in the input RF signal is bypassed to the ground through the resistor (Shen, Paragraph 21, lines 25-28).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 3, Takenaka fails to disclose:
wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal.
However, Shen further teaches wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal (Shen, Paragraph 21, lines 25-28).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 4, Takenaka fails to disclose:
wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor.
However, Shen further teaches wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor (Shen, Fig. 2, see path from MIC1 to MICN via C15).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 6, Takenaka further discloses:
further comprising: a second power transistor (Takenaka, Fig. 1, 12, see also Paragraph 52, lines 1-10) comprising an input terminal (Fig. 1, see input of 12) and an output terminal connected to an output terminal of the first power transistor (Fig. 1, see connection between output of 12 and 102); but fails to disclose and a second capacitor connected between the first end of the resistor and the input terminal of the second power transistor.
However, Shen further teaches and a second capacitor (Shen, Fig. 2, C14) connected between the first end of the resistor and the input terminal of the second power transistor (Fig. 2, see connection between MICP and R8 via C14 and MIC1).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 7, Takenaka fails to disclose:
wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor, and passes through the second capacitor to be input to the input terminal of the second power transistor.
However, Shen further teaches wherein the input RF signal passes through the first capacitor to be input to the input terminal of the first power transistor (Shen, Fig. 2, see connection between MIC1 and MICN via C15), and passes through the second capacitor to be input to the input terminal of the second power transistor (Fig. 2, see connection between MIC1 and MICP via C14).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 8, Takenaka further discloses:
further comprising: a first bias circuit (Takenaka, Fig. 1, 104) configured to supply a first bias current to the input terminal of the first power transistor (Paragraph 50, lines 7-10); and a second bias circuit (Fig. 1, 104) configured to supply a second bias current to the input terminal of the second power transistor (Paragraph 50, lines 7-10).
Regarding claim 11, Takenaka fails to disclose:
wherein a low-frequency signal comprising a noise included in the first differential signal is bypassed to the ground through the first resistor, and a low-frequency signal comprising a noise included in the second differential signal is bypassed to the ground through the second resistor.
However, Shen further teaches wherein a low-frequency signal comprising a noise included in the first differential signal is bypassed to the ground through the first resistor (Shen, Paragraph 21, lines 25-28), and a low-frequency signal comprising a noise included in the second differential signal is bypassed to the ground through the second resistor (Paragraph 21, lines 25-28, see also Fig. 2, connection between R6 and ground via C10).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 12, Takenaka fails to disclose:
wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and the common mode signal.
However, Shen further teaches wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and the common mode signal (Shen, Paragraph 21, lines 25-28).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 13, Takenaka fails to disclose:
wherein the first differential signal passes through the first capacitor to be input to the input terminal of the first power transistor, and the second differential signal passes through the second capacitor to be input to the input terminal of the second power transistor.
However, Shen further teaches wherein the first differential signal passes through the first capacitor to be input to the input terminal of the first power transistor (Shen, Fig. 2, see connection between MIC1 and MICN via C15), and the second differential signal passes through the second capacitor to be input to the input terminal of the second power transistor (Fig. 2, see connection between MIC1 and MICP via C14).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 16, Takenaka fails to disclose:
wherein a low-frequency signal included in the input RF signal is bypassed to the ground through the second element.
However, Shen further teaches wherein a low-frequency signal included in the input RF signal is bypassed to the ground through the second element (Shen, Paragraph 21, lines 25-28).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 17, Takenaka fails to disclose:
wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal.
However, Shen further teaches wherein the low-frequency signal comprises either one or both of a low-frequency noise signal and a common mode signal (Shen, Paragraph 21, lines 25-28).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Regarding claim 18, Takenaka fails to disclose:
wherein the input RF signal passes through the first element to be input to the first input terminal of the first power transistor.
However, Shen further teaches wherein the input RF signal passes through the first element to be input to the first input terminal of the first power transistor (Shen, Fig. 2, see path from MIC1 to MICN via C15).
Takenaka, Phelps, and Shen are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Takenaka to incorporate the teachings of Shen to include the RC network of Shen in the circuit of Takenaka, which would have the effect of filtering out low-frequency noise (Shen, Paragraph 21, lines 25-28).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (Patent Publication Number CN 107,861,899 A) discloses (Fig. 2) an RC network for removing low-frequency noise.
Sugiyama et al. (Patent Number JP 5,488,955 B2) discloses (Fig. 5) an input RC network for removing low-frequency noise.
Gunaa (Patent Number JP S60,233,920 A) discloses (Fig. 1) an amplifier with two parallel paths having resistors that couple amplifier inputs to ground.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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