Prosecution Insights
Last updated: October 02, 2026
Application No. 18/217,056

FORMING POROUS DIELECTRIC STRUCTURES WITH SPATIALLY-CONTROLLED POROSITY

Non-Final OA §102§103
Filed
Jun 30, 2023
Examiner
ANYA, IGWE U
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
817 granted / 961 resolved
+25.0% vs TC avg
Minimal -4% lift
Without
With
+-3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
970
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
36.6%
-3.4% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 961 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 4, 9 and 12 – 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chikaki et al. (US 2012/0025395). PNG media_image1.png 458 482 media_image1.png Greyscale (Claim 1) Chikaki et al. teach an apparatus comprising: one or more integrated circuit (IC) package metallization levels comprising metallization features; a dielectric material (6/7) adjacent to one more of the metallization features, the dielectric material comprising a matrix material and a surfactant (paragraphs 37, 43, 55, 56); and a plurality of substantially spherical pores within the matrix material, wherein the substantially spherical pores are surrounded by an outer shell comprising the matrix material (paragraphs 55, 56). (Claim 2) Chikaki et al. teach wherein a first portion of the dielectric material comprises a first (7) pore density and a second (6) portion of the dielectric material comprises a second pore density. (Claim 3) Chikaki et al. teach wherein the first (7) pore density is not less than twice the second (6) pore density (paragraph 43). (Claim 4) Chikaki et al. teach wherein the second portion comprises a dielectric constant that is not less than 1.5 times greater than a dielectric constant of the first portion (paragraphs 22, 44, 76). (Claim 9) Chikaki et al. teach wherein the apparatus comprises a build-up layer of a microelectronic package structure, wherein a first metallization (11) feature of the metallization features is within a first region (7) of the build-up layer, the first region comprising a first pore density (paragraph 43), and wherein a second metallization feature (10) of the metallization features is within a second region (6) of the build-up layer, the second region comprising a second pore density (paragraph 43), wherein the first pore density is not less than 1.5 times greater than the second pore density (paragraphs 22, 43, 44, 76). (Claim 12) Chikaki et al. teach a system, comprising: a substrate (10); a dielectric material (6/7) on the substrate, the dielectric material comprising a matrix material and a surfactant (paragraphs 37, 43, 55, 56); a plurality of pores within the dielectric material, wherein an outer shell surrounding individual ones of the plurality of pores comprises the matrix material (paragraphs 55, 56), wherein: a first region (7) of the dielectric material comprising a first pore density, and a second region (6) of the dielectric material adjacent to the first region, comprises a second pore density (paragraph 43), not less than 1.5 times the first pore density; and a device over the substrate (not shown, paragraph 72). (Claim 13) Chikaki et al wherein a power supply is coupled to the device, and wherein the dielectric material comprises a portion of a build-up layer (paragraph 72) (Claim 14) Chikaki et al wherein the dielectric material (6/7) is between a first conductive trace (3) and a second conductive trace (paragraph 40). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 5 and 17 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chikaki et al. (US 2012/0025395) in view of Yamamoto (US 2006/0116000) (Claim 5) Chikaki et al. lack wherein a diameter of an individual spherical pore of the plurality of substantially spherical pores comprises between 1 nm to 10 microns. However, Yamamoto teaches wherein a diameter of an individual spherical pore of the plurality of substantially spherical pores comprises between 1 nm to 2 microns for the benefit of reducing uneven film thickness distribution and variations in the relative dielectric constant of the insulating film (paragraph 82). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of reducing uneven film thickness distribution and variations in the relative dielectric constant of the insulating film. (Claim 17) Chikaki et al. teach an assembly, comprising: a dielectric material comprising a plurality of pores, a first region and a second region of the dielectric material, wherein the first region comprises a first pore density and the second region comprises a second pore density, wherein the first pore density is greater than two times the second pore density; and a device over the dielectric material. Chikaki et al. lack wherein individual pores of the plurality of pores comprise a pore diameter between 1 nm and 10 microns. However, Yamamoto teaches wherein individual pores of the plurality of pores comprise a pore diameter between 1 nm and 2 microns for the benefit of reducing uneven film thickness distribution and variations in the relative dielectric constant of the insulating film (paragraph 82). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of reducing uneven film thickness distribution and variations in the relative dielectric constant of the insulating film. (Claim 18) Chikaki et al. teach wherein one or more integrated circuit (IC) package metallization levels comprising metallization features (3) are adjacent the dielectric material (paragraph 72). (Claim 19) Chikaki et al. teach wherein the first region (7) comprises a first dielectric constant and the second region (6) comprises a second dielectric constant, wherein the second dielectric constant is at least ten percent greater than the first dielectric constant (paragraph 72). (Claim 20) Chikaki et al. lack wherein the apparatus comprises a build-up layer of a microelectronic package structure. However, Yamamoto teaches wherein the apparatus comprises a build-up layer of a microelectronic package structure as art recognized equivalents (paragraph 28). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents Allowable Subject Matter Claims 6 – 8, 10 – 11 and 15 – 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Claim 6) wherein the first layer comprises the matrix material and is free of the surfactant; and wherein a thickness of the first layer is between 0.5 microns to 5 microns. Conclusion Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IGWE U ANYA/Primary Examiner, Art Unit 2891 August 8, 2026
Read full office action

Prosecution Timeline

Jun 30, 2023
Application Filed
Nov 08, 2023
Response after Non-Final Action
Aug 12, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
81%
With Interview (-3.7%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 961 resolved cases by this examiner. Grant probability derived from career allowance rate.

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