DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 12/11/25, for application number 18/217,274 has been received and entered into record. Claims 1, 4, 6-11, 15, 18-20, and 23 have been amended, Claims 2, 3, 16, and 17 have been cancelled, and Claims 24-27 have been newly added. Therefore, Claims 1, 4-15, and 18-27 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 11, 15, 18, and 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Han, US 2021/0365095 A1, in view of Fan et al., US 9,009,500 B1, and further in view of Che et al., US 2022/0335003 A1.
Regarding Claim 1, Han discloses an integrated circuit (IC) chip [integral chassis of Fig. 2] comprising:
a plurality of nodes in a network [nodes A-D];
a first aggregation zone comprising a first node and a second node, wherein:
each node of the plurality of nodes comprises: an aggregation circuit configured to receive a first indication of power consumption associated with each node [in each node, the BMC accumulates the power consumption of all the corresponding PSUs for query by the CMC (BMC being the aggregation circuit), par 50]; and
the aggregation circuit in each of the first node and the second node is configured to reduce power consumption in its respective node in response to the first control signal [according to the embodiment, the CMC is able to dynamically adjust the actual power consumption of nodes inside the integral chassis based on the amount of services of the nodes. When a node has less service, power consumption of the node may be automatically reduced by means of frequency reduction or the like, which effectively reduces unnecessary power consumption such as heat and thus improves node efficiency, par 77].
However, Han does not explicitly teach a plurality of nodes in a mesh network; and a first aggregation zone comprising a locally-formed subset of the plurality of nodes; and a configuration register configured to selectively control the aggregation circuit to operate as a zone leader node or a zone follower node; the aggregation circuit in the first node is configured to, in response to the configuration register storing configuration data that the first node is to operate as the zone leader node; receive, from the second node, a second indication of power consumption associated with the second node operating as zone follower node within the first aggregation zone; and provide a first control signal based on the first indication of power consumption and the second indication of power consumption to each zone follower node within the first aggregation zone; and wherein the first control signal is distributed only within the first aggregation zone.
In the analogous art of mesh network power management, Fan teaches a plurality of nodes in a mesh network; and a first aggregation zone comprising a locally-formed subset of the plurality of nodes [power management modules (PMMs) measuring the amount of power consumed by their respective child nodes (the PMMs and their respective child nodes being a localized zone), Fig. 1, 3; col. 4, ll. 54-66]; receive, from the second node, a second indication of power consumption associated with the second node operating as zone follower node within the first aggregation zone; provide a first control signal based on the first indication of power consumption and the second indication of power consumption to each zone follower node within the first aggregation zone [PMMs can communicate with each other to allocate power from a shared supply; communication can be over a peer-to-peer network, col. 4, ll. 54-59]; wherein the first control signal is distributed only within the first aggregation zone [PMMs may generate a request message asking child nodes to limit or reduce their present power consumption (i.e. only sending power reduction signal to their localized zone), col. 4, ll. 4-9].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han and Fan before him before the effective filing date of the claimed invention, to incorporate the power consumption reduction as taught by Fan, into the chip as disclosed by Han, to ensure appropriate current flow [Fan, col. 1, ll. 18-30].
However, the combination of Han and Fan do not explicitly teach a configuration register configured to selectively control the aggregation circuit to operate as a zone leader node or a zone follower node; the aggregation circuit in the first node is configured to, in response to the configuration register storing configuration data that the first node is to operate as the zone leader node.
In the analogous art of node management, Che teaches a configuration register configured to selectively control the aggregation circuit to operate as a zone leader node or a zone follower node; the aggregation circuit in the first node is configured to, in response to the configuration register storing configuration data that the first node is to operate as the zone leader node [FIG. 4 illustrates an embodiment of a master-slave system 400 that creates a subdomain using registers configured as master-slave nodes. Master-slave system 400 includes global master node 402, slave node 404, and slave node 406, par 20].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han, Fan, and Che before him before the effective filing date of the claimed invention, to incorporate the configuration register as taught by Che, into the chip as disclosed by Han and Fan, to improve performance and efficiency by allow for direct communication of nodes [Che, par 13].
Regarding Claim 4, Han, Fan, and Che disclose the IC chip of Claim 1. Han further discloses a second aggregation zone comprising a third node and a fourth node [nodes A-D, Fig. 2], wherein: the aggregation circuit in the third node is configured to operate in a first mode; and the aggregation circuit in each of the third node and a fourth node is configured to reduce power consumption in its respective node in response to a second control signal provided by the third node [according to the embodiment, the CMC is able to dynamically adjust the actual power consumption of nodes inside the integral chassis based on the amount of services of the nodes. When a node has less service, power consumption of the node may be automatically reduced by means of frequency reduction or the like, which effectively reduces unnecessary power consumption such as heat and thus improves node efficiency, par 77], and Che further discloses configuring aggregation circuits as a zone leader node or a zone follower node [FIG. 4 illustrates an embodiment of a master-slave system 400 that creates a subdomain using registers configured as master-slave nodes. Master-slave system 400 includes global master node 402, slave node 404, and slave node 406, par 20].
Regarding Claim 11, Han, Fan, Che, and Long disclose the IC chip of Claim 1. Han further discloses wherein the mesh network extends over a first area of the IC chip [integral chassis of Fig. 2, with the nodes extending over the chip].
However, the combination of references does not explicitly teach wherein the first node is disposed in a center portion of the first area.
Examiner notes, however, devices which operate “on basically the same principle and in the same manner” where the differences, in addition to being well-known, “solve no stated problem and would be an obvious matter of design choice within the skill of the art” are obvious variations of one another and thus not patentably distinct. See In re Kuhle, 188 USPQ 7 (CCPA 1975). As such, the location of the first node being disposed in a center portion of a first area appears to simply be a design choice, and would perform the same function regardless of position.
Regarding Claim 15, Han discloses a method in an integrated circuit (IC) chip [using the device of Fig. 2, performing the method of Fig. 1]. The remainder of Claim 15 recites limitations similar to those recited in Claim 1, and is rejected accordingly.
Regarding Claim 18, Han, Fan, and Che disclose the method of Claim 15. Claim 18 repeats the same limitations as recited in Claim 4, and is rejected accordingly.
Regarding Claim 24, Han discloses an integrated circuit (IC) chip having a plurality of nodes [integral chassis of Fig. 2 with nodes A-D], the chip comprising: a first node in a first aggregation zone [in each node, the BMC accumulates the power consumption of all the corresponding PSUs for query by the CMC (BMC being the aggregation circuit), par 50], the first node comprising: the first aggregation circuit configured to receive a first indication of power consumption associated with the first node; and a second node in the first aggregation zone, the second node comprising: a second aggregation circuit configured to: receive a second indication of power consumption associated with the second node; and provide a first control signal based on the first indication of power consumption and the second indication of power consumption to the second node, the first control signal instructing the first aggregation circuit and the second aggregation circuit to reduce power consumption of the first node and the second node, respectively [according to the embodiment, the CMC is able to dynamically adjust the actual power consumption of nodes inside the integral chassis based on the amount of services of the nodes. When a node has less service, power consumption of the node may be automatically reduced by means of frequency reduction or the like, which effectively reduces unnecessary power consumption such as heat and thus improves node efficiency, par 77].
However, Han does not explicitly teach a plurality of nodes in a mesh network; a first configuration register configured to selectively control a first aggregation circuit to operate as a zone leader node; the second node being connected to the first node via a mesh network; a second configuration register configured to selectively control a second aggregation circuit to operate as a zone follower node; provide the second indication of power consumption to the first node; and wherein the first aggregation circuit is further configured to: receive, from the second node, the second indication of power consumption.
In the analogous art of mesh network power management, Fan teaches a plurality of nodes in a mesh network; and the second node being connected to the first node via a mesh network [power management modules (PMMs) measuring the amount of power consumed by their respective child nodes (the PMMs and their respective child nodes being a localized zone), Fig. 1, 3; col. 4, ll. 54-66]; provide the second indication of power consumption to the first node; and wherein the first aggregation circuit is further configured to: receive, from the second node, the second indication of power consumption [PMMs can communicate with each other to allocate power from a shared supply; communication can be over a peer-to-peer network, col. 4, ll. 54-59].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han and Fan before him before the effective filing date of the claimed invention, to incorporate the power consumption reduction as taught by Fan, into the chip as disclosed by Han, to ensure appropriate current flow [Fan, col. 1, ll. 18-30].
However, the combination of Han and Fan do not explicitly teach a first configuration register configured to selectively control a first aggregation circuit to operate as a zone leader node; and a second configuration register configured to selectively control a second aggregation circuit to operate as a zone follower node.
In the analogous art of node management, Che teaches a first configuration register configured to selectively control a first aggregation circuit to operate as a zone leader node; and a second configuration register configured to selectively control a second aggregation circuit to operate as a zone follower node [FIG. 4 illustrates an embodiment of a master-slave system 400 that creates a subdomain using registers configured as master-slave nodes. Master-slave system 400 includes global master node 402, slave node 404, and slave node 406, par 20].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han, Fan, and Che before him before the effective filing date of the claimed invention, to incorporate the configuration register as taught by Che, into the chip as disclosed by Han and Fan, to improve performance and efficiency by allow for direct communication of nodes [Che, par 13].
Regarding Claim 25, Han, Fan, and Che disclose the chip of Claim 24. Fan further teaches wherein the first control signal is distributed only within the first aggregation zone [PMMs may generate a request message asking child nodes to limit or reduce their present power consumption (i.e. only sending power reduction signal to their localized zone), col. 4, ll. 4-9].
Regarding Claim 26, Han, Fan, and Che disclose the IC chip of Claim 24. Claim 26 recites limitations similar to those of Claims 4 and 24, and are rejected accordingly.
Regarding Claim 27, Han, Fan, and Che disclose the IC chip of Claim 24. Fan further teaches wherein the first aggregation zone comprises a locally-formed subset of the plurality of nodes on the IC chip [power management modules (PMMs) measuring the amount of power consumed by their respective child nodes (the PMMs and their respective child nodes being a localized zone), Fig. 1, 3; col. 4, ll. 54-66].
Claims 5-9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Han, Fan, and Che, and further in view of Long et al., US 2019/0165575 A1.
Regarding Claim 5, Han, Fan, and Che disclose the IC chip of Claim 1. However, the combination of references does not explicitly teach wherein: the mesh network further comprises segments, each coupled between two nodes of the plurality of nodes adjacent to each other; and each node of the plurality of nodes is coupled to at least two segments of the mesh network.
In the analogous art of node power management, Long teaches wherein: the mesh network further comprises segments, each coupled between two nodes of the plurality of nodes adjacent to each other; and each node of the plurality of nodes is coupled to at least two segments of the mesh network [nodes of Fig. 7 may be grouped into various “segments”, Fig. 7].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han, Fan, Che, and Long before him before the effective filing date of the claimed invention, to incorporate the power monitoring as taught by Long, into the chip as disclosed by Han, Fan, and Che, to overcome the limits of being tethered to a central power manager [Long, par 6].
Regarding Claim 6, Han, Fan, Che, and Long disclose the IC chip of Claim 5. Long further teaches wherein the first node in the first aggregation zone is adjacent to the second node [nodes adjacent to one another, Fig. 7].
Regarding Claim 7, Han, Fan, Che, and Long disclose the IC chip of Claim 6. Long further teaches wherein the mesh network comprises the second node and three other nodes all adjacent to the first node [nodes adjacent to one another, Fig. 7].
Regarding Claim 8, Han, Fan, Che, and Long disclose the IC chip of Claim 7. Long further teaches wherein the aggregation circuit in the first node is further configured to identify the second node as one node among a plurality of nodes adjacent to the first node [Each power node (101), (102) and (103) includes a communication interface device e.g. a network interface device operable to establish a communication network (120) that includes other power nodes and to exchange command and control signals and data with all other power nodes associated with the distributed power network (100); (exchanging command and control signals and data with other nodes would necessarily require identifying the nodes in the mesh network in order to perform the exchange), par 22, ll. 6-12].
Regarding Claim 9, Han, Fan, Che, and Long disclose the IC chip of Claim 6. Han further discloses provide the first control signal to the fifth node; and the first node is further configured to provide the first control signal based on the third indication of power consumption [according to the embodiment, the CMC is able to dynamically adjust the actual power consumption of nodes inside the integral chassis based on the amount of services of the nodes. When a node has less service, power consumption of the node may be automatically reduced by means of frequency reduction or the like, which effectively reduces unnecessary power consumption such as heat and thus improves node efficiency, par 77]. Long further teaches the first aggregation zone further comprises at least a fifth node that is adjacent to the second node; the aggregation circuit in the second node is configured to: receive a third indication of power consumption associated with the fifth node; and provide the third indication of power consumption to the first node [each node has a processor and can run the energy management schema to compute the elements of control for itself as well as the elements of control for all other power nodes on the network (100). Since all power nodes include the same energy management schema and the same information, each power node (205) can determine the elements of control for itself and for each of the other power nodes, and act accordingly, Fig. 2; par 44].
Regarding Claim 19, Han, Fan, and Che disclose the method of Claim 15. Claim 19 repeats the same limitations as recited in Claim 9, and is rejected accordingly.
Claims 12-14 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Han, Fan, and Che, and further in view of Yeager et al., US 2019/0094939 A1.
Regarding Claim 12, Han, Fan, and Che disclose the IC chip of Claim 1. However, the combination of references does not explicitly teach a voltage comparator configured to compare a power supply voltage to a threshold, wherein in each node of the plurality of nodes, the first indication of power consumption associated with the node comprises an output from the voltage comparator.
In the analogous art of power management, Yeager teaches a voltage comparator configured to compare a power supply voltage to a threshold, wherein in each node of the plurality of nodes, the first indication of power consumption associated with the node comprises an output from the voltage comparator [the present voltage level of the node as compared to a voltage set point may be used to determine transaction scaling; the transaction scaler 902 may receive information from the operating metrics acquisitions module 904 such as the operating metrics information that includes one or more sensed inputs. Examples of sensed input information, which should not be considered limiting, include aggregate VC[*] activity per port, adjacent node clock-gating, operating frequency and/or voltage of the node 400; power consumed by network on chip (NOC) based on operating voltages, par 45, ll. 4-6; par 58; par 4].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han, Fan, Che, and Yeager before him before the effective filing date of the claimed invention, to incorporate the voltage detection as taught by Yeager into the chip as disclosed by Han, Fan, and Che, to achieve a desired frequency of operation with reasonable power consumption [Yeager, par 4].
Regarding Claim 13, Han, Fan, and Che disclose the IC chip of Claim 1. However, the combination of references does not explicitly teach wherein: at least one node of the plurality of nodes is coupled to a corresponding processing circuit; and in the at least one node coupled to a corresponding processing circuit, the first indication of power consumption associated with the node comprises an indication from the corresponding processing circuit of an event related to a data transmission.
In the analogous art of power management, Yeager teaches wherein: at least one node of the plurality of nodes is coupled to a corresponding processing circuit; and in the at least one node coupled to a corresponding processing circuit, the first indication of power consumption associated with the node comprises an indication from the corresponding processing circuit of an event related to a data transmission [the transaction scaler 902 may receive information from the operating metrics acquisitions module 904 such as the operating metrics information that includes one or more sensed inputs. Examples of sensed input information, which should not be considered limiting, include aggregate VC[*] activity per port, adjacent node clock-gating, operating frequency and/or voltage of the node 400 (the activity being data transmission); power consumed by network on chip (NOC) is based on operating voltages, par 58, 4].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han, Fan, Che, and Yeager before him before the effective filing date of the claimed invention, to incorporate the power monitoring as taught by Yeager into the chip as disclosed by Han, Fan, and Che, to achieve a desired frequency of operation with reasonable power consumption [Yeager, par 4].
Regarding Claim 14, Han, Fan, and Che disclose the IC chip of Claim 1. However, the combination of references does not explicitly teach wherein: each node of the plurality of nodes further comprises a plurality of router circuits configured to transmit data on a segment of the mesh network; and in each node of the plurality of nodes, reducing power consumption in the node comprises inhibiting data transmissions from at least a subset of the plurality of router circuits in the node.
In the analogous art of power management, Yeager teaches wherein: each node of the plurality of nodes further comprises a plurality of router circuits [network on chip (NOC) with routing nodes, Fig. 1] configured to transmit data on a segment of the mesh network; and in each node of the plurality of nodes, reducing power consumption in the node comprises inhibiting data transmissions from at least a subset of the plurality of router circuits in the node [the transaction scaler 902 may receive information from the operating metrics acquisitions module 904 such as the operating metrics information that includes one or more sensed inputs. Examples of sensed input information, which should not be considered limiting, include aggregate VC[*] activity per port, adjacent node clock-gating, operating frequency and/or voltage of the node 400; transaction scaler throttles the transactions, which would reduce power consumption due to less activity, par 58, 39].
It would have been obvious to one of ordinary skill in the art, having the teachings of Han, Fan, Che, and Yeager before him before the effective filing date of the claimed invention, to incorporate the power management as taught by Yeager into the chip as disclosed by Han, Fan, and Che, to achieve a desired frequency of operation with reasonable power consumption [Yeager, par 4].
Regarding Claims 21-23, Han, Fan, and Che disclose the method of Claim 15. Claims 21-23 repeat the same limitations as recited in Claims 12-14, respectively, and are rejected accordingly.
Response to Arguments
Applicant’s arguments filed 12/11/25 have been considered but are moot due to the new rejection based on the references cited above, as well as the newly cited portions of the references previously presented.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175