DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/30/2023, 06/25/2024, and 09/09/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 3, 7, 12-13, 15, and 17 are objected to because of the following informalities:
Claim 3- “the branch” should be “the current branch” to be consistent with claim 1 which introduces “a current branch”
Claim 7- replace “to be” with --being-- to improve grammar
Claim 12- “the thread execution of the single thread” should be “the execution of the single thread” to be consistent with claim 1 which introduces “execution of a single thread”
Claim 13 line 5- “the thread execution” should be “the execution” to be consistent
Claim 15- “the branch” should be “the current branch” to be consistent with claim 13 which introduces “a current branch”
Claim 17 line 2- replace “are capable of causing” with --causes-- to improve clarity
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “their corresponding thresholds” in line 7. There is insufficient antecedent basis for this limitation as the claim does not introduce thresholds corresponding to the branch misprediction rate, microinstruction waste rate, and cache missing rate. For purposes of examination this will be interpreted as any corresponding thresholds.
Claims 13 and 17 recite the same limitation and are rejected for the same reasons.
Claim 1 recites “one or more thresholds for the branch misprediction rate, the microinstructions waste rate, and the cache missing rate of the single thread” in lines 9-11. It is unclear whether this is the same as the corresponding thresholds referenced in line 7 or if they are different. For purposes of examination, they will be interpreted as the same.
Claims 13 and 17 recite the same limitation and are rejected for the same reasons.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sheikh US 2017/0090936.
Regarding claim 1, Sheikh teaches:
1. A method ([0006] discloses a method for controlling application of a predictor based on a predictor effectiveness measurement) comprising:
determining, based on looking up a branch confidence data structure, whether a current branch in execution of a single thread is a low confidence branch in which a branch predictor of a processor has a low level of certainty that outcome of the current branch is predicted correctly (this limitation is not required under BRI of a method claim since it is contingent on looking up a branch confidence data structure, which is not required by the claim; for example, while [0059] discloses that the BCDS may be looked up on every branch prediction, [0073] discloses that rather than looking up the predictor every cycle, the processor may have inactive cycles, which suggests that the looking up of the branch confidence data structure (and thus the determining step) does not always occur (i.e., the determining step is contingent on the lookup occurring); Examiner suggests positively reciting a step of looking up the branch confidence data structure before this limitation to require the determining step to occur and amending the other independent claims similarly for consistency);
comparing a branch misprediction rate, a microinstruction waste rate, and a cache missing rate of the single thread with their corresponding thresholds (this limitation is not required since it follows from a contingent limitation that is not required under BRI); and
throttling branch prediction of the current branch based on the determination of the current branch being a low confidence branch and one or more thresholds for the branch misprediction rate, the microinstructions waste rate, and the cache missing rate of the single thread being crossed (this limitation is not required since it follows from a contingent limitation that is not required under BRI and is further contingent on one or more thresholds being crossed, which is not required by the claim).
Regarding claim 2, Sheikh teaches:
2. The method of claim 1, wherein looking up the branch confidence data structure occurs when the processor performs branch prediction (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 3, Sheikh teaches:
3. The method of claim 1, wherein the branch confidence data structure includes an entry for the current branch, and the entry includes an identifier of the branch and an indication of low confidence (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 4, Sheikh teaches:
4. The method of claim 3, wherein the entry further includes (this limitation is not required since it follows from a contingent limitation that is not required under BRI) one or more of:
a number of branch predictions that have been done for the current branch, and
a count of mis-prediction or a successful prediction within the branch predictions.
Regarding claim 5, Sheikh teaches:
5. The method of claim 1, wherein throttling the branch prediction comprises (this limitation is not required since it follows from a contingent limitation that is not required under BRI) one or more of:
skipping operations for a number of clock cycles in one or more stages of an execution pipeline of the processor,
reducing a rate of operations in one or more stages of the execution pipeline of the processor, or
limiting a number of in-flight instructions in the execution pipeline of the processor.
Regarding claim 6, Sheikh teaches:
6. The method of claim 1, wherein a level of throttling the branch prediction is based on a performance state of the processor (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 7, Sheikh teaches:
7. The method of claim 6, wherein the performance state of the processor being lower than a default performance state corresponds to the level of throttling to be higher than a default level of throttling (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 8, Sheikh teaches:
8. The method of claim 6, wherein the level of throttling is determined based on a mapping between the performance state of the processor and the level of throttling (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 9, Sheikh teaches:
9. The method of claim 1, wherein the branch misprediction rate of the single thread is determined based on a number of mis-predicted microoperations per a number of clock cycles (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 10, Sheikh teaches:
10. The method of claim 1, wherein the microinstruction waste rate of the single thread is determined based on a ratio of allocated microoperations and retired microoperations (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 11, Shiekh teaches:
11. The method of claim 1, wherein the cache missing rate of the single thread is determined based on a number of cache misses per a number of instructions (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 12, Sheikh teaches:
12. The method of claim 1, further comprising:
removing the branch prediction throttling, once the thread execution of the single thread is no longer in a low confidence branch (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Prior Art Considerations
While no prior art rejection is given for claims 13-20, these claims are currently rejected under 112(b) and are not allowable at the current point. The following prior art considerations are given for these claims:
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claims, determining whether a current branch of a single thread is a low-confidence branch based on looking up a branch confidence data structure, comparing a branch misprediction rate, a microinstruction waste rate, and a cache missing rate of the single thread with corresponding thresholds and throttling branch prediction of the current branch based on the determination and one or more thresholds for the branch misprediction rate, microinstructions waste rate, and cache missing rate being crossed, as required in claims 13 and 17.
The closest prior art of record was found to be:
US 2017/0090936 (hereinafter, Sheikh) which teaches comparing predictor effectiveness measurements for each instruction signature to a threshold and enabling/disabling the predictor based on the comparison, see Fig. 3, where the effectiveness may be a measure of the predictor misprediction rate, see [0027].
US 2012/0227045 (hereinafter, Knauth) which teaches throttling speculative execution if the difference between a cumulative event count of committed and uncommitted execution indicating wasted execution is above a threshold, see [0075], where the events may include cache misses or branch mispredictions, see [0035].
US 2021/0019150 (hereinafter, Schinzler) which teaches throttle control circuitry that throttles speculative instruction issue rate based on confidence level of how likely a branch prediction is to be correct and based on instruction flush/waste rate, see [0017], [0023], and Fig. 3.
US 2019/0332380 (hereinafter, Bhat) teaches dynamically adjusting a threshold used for classifying branches as hard to predict based on a workload, see Abstract, which may involve looking up entries in a branch classification table, see [0011]
While the prior art was found to generally teach determining whether a branch is low confidence based on looking up a data structure (Bhat) and throttling branch prediction or speculative execution based on various conditions (Sheikh, Knauth, Schinzler), the prior art was not found to teach and/or fairly suggest the specific combination of features found in claims 13 and 17 which describes throttling branch prediction based on determining that a branch is low confidence (based on looking up a branch confidence data structure) and thresholds for three specific rates (i.e., a branch misprediction rate, microinstruction waste rate, and a cache missing rate) being crossed. Further, it would not have been obvious to one of ordinary skill in the art to combine the prior art in a way that would arrive at the claimed invention of claims 13 and 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2009/0150657 teaches throttling instruction fetch when a cumulative confidence for a branch instruction group is below a first threshold and inhibiting the throttling when the confidence for a currently issued branch instruction is less than a second threshold, see Fig. 4
US 2013/0145135 teaches reducing speculation if CPI is below a CPI threshold and the number of memory accesses per unit time is above a threshold, see Abstract
US 2015/0301832 teaches calculating a misprediction threshold based on the number of branches and a predefined misprediction ratio and disabling branch prediction based on the number of mispredictions exceeding the threshold and dependent upon the branch rate, see Abstract
US 2017/0249149 teaches throttling instructions in a pipeline stage based on a comparison of a weight sum of confidence levels with a threshold, see Abstract
US 2012/0102269 teaches issuing speculative requests for instructions that are likely to miss in multiple cache levels, see [0031]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KASIM ALLI whose telephone number is (571)270-1476. The examiner can normally be reached Monday - Friday 9am 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KASIM ALLI/Examiner, Art Unit 2183
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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