DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
In summary, claim 17 recites a “machine-readable medium” storing instructions that perform various functions. The specification of the present application states, a machine-readable media may be “a non-transitory computer machine-readable storage media” or “a transitory computer machine-readable communication media” (see Paragraph [0159]). Thus, the broadest, reasonable interpretation of “machine-readable medium” in view of the specification encompasses non-statutory subject matter that is unpatentable under 35 U.S.C. 101 (see MPEP 2106.03(I)). The examiner suggests amending the claim to recite a “non-transitory” machine-readable storage medium.
Accordingly, Claim 17 fails to recite statutory subject matter under 35 U.S.C. 101. Claims 18-20 depend on and do not cure the deficiencies of claim 17—therefore claims 18-20 are also directed to non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-7, 9-11, 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Non-patent literature by Jenkins et al., “Combined System-Level Redundancy and Modular Arithmetic for Fault Tolerant Digital Signal Processing” [hereafter Jenkins], and further in view of Ren et al. (PG Pub. 2023/0,251,941) [hereafter Ren].
As per claim 1, Jenkins teaches:
An apparatus, comprising: three processing elements operable in a first redundancy mode, the three processing elements to execute a same sequence of instructions to produce three corresponding results; (Jenkins, pg. 29, col. 2, 1st paragraph of Section 3, triple modular redundancy (TMR))
detection circuitry to detect when any one processing element of the three processing elements produces a different result from the other two processing elements of the three processing elements; (Jenkins, pg. 29, col. 2, 1st paragraph of Section 3, in TMR, results from 3 separate computers are compared to see if any one of them are faulty)
tracking circuitry to associate an error with the one processing element when it produces the different result from the other two processing elements, (Jenkins, pg. 29, col. 2, 1st paragraph of Section 3, one of the three are considered faulty when one system consistently disagrees; to determine whether it is consistently disagreeing, errors must be tracked)
when the one processing element is determined to be faulty, the other two processing elements are to operate in a second redundancy mode excluding the one processing element (Jenkins, pg. 29, col. 2, 1st paragraph of Section 3, the system determined to be faulty is removed from consideration and reliability is maintained by continuing to compare the results of the remaining two properly functioning system)
Jenkins does not specifically teach:
determining if an error threshold is reached of a processing element to determine the processing element to be faulty
However, Ren in an analogous art teaches:
determining if an error threshold is reached of a processing element (Ren, ¶ [0061], a number of such errors exceeding a threshold value, a number of errors exceeding a threshold value with a specified time period)
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Ren into the method of Jenkins to provide a method of determining if an error threshold is reached of a processing element to determine the processing element to be faulty. The modification would be obvious because such information allows system to decide on when to declare the node is considered to be faulty (Ren, ¶ [0061]).
As per claim 2, the rejection of claim 1 is incorporated and Ren further teaches:
wherein the tracking circuitry is to accumulate errors associated with each processing element of the three processing elements and to determine when the error threshold is reached for any processing element of the three processing elements (Ren, ¶ [0061], a number of such errors exceeding a threshold value, a number of errors exceeding a threshold value with a specified time period)
As per claim 5, the rejection of claim 1 is incorporated and Ren further teaches:
wherein the second redundancy mode of the other two processing elements comprises a lockstep mode in which an error is generated in response to detecting a difference between a first result produced by a first processing element of the two processing elements and a second result produced by a second processing element of the two processing elements (Jenkins, pg. 29, col. 2, 1st paragraph of Section 3, “Reliability is maintained by continuing to compare the results of the remaining two properly functioning systems”; occurrence of a second failure)
As per claim 6, the rejection of claim 5 is incorporated and Ren further teaches:
wherein if error correction was used to produce one of the first result or the second result, then the tracking circuitry is to associate an error with the result for which the error correction was used (Jenkins, pg. 29, col. 2, 1st paragraph of Section 3, “If the two functioning systems eventually cease to agree, then a second failure has occurred, and some type of off-line diagnostics can be invoked to determine which of the two has failed”)
As per claim 7, the rejection of claim 6 is incorporated and Jenkins further teaches:
wherein if he first processing element or the second processing element is determined to be faulty, then the corresponding one of the first processing element and the second processing element is removed from participating in the lockstep mode and the other one of the first processing element and the second processing element is to continue to operate (Jenkins, pg. 29, col. 2, 1st paragraph of Section 3, “If the two functioning systems eventually cease to agree, then a second failure has occurred, and some type of off-line diagnostics can be invoked to determine which of the two has failed. Once the faulty system is identified and removed from further voting, the computational process can continue on the remaining functioning computer.”)
In addition, Ren further teaches:
wherein the error threshold comprises a first error threshold, wherein if a second error threshold associated with the first processing element or the second processing element is reached, determining the first processing element or the second processing element to be faulty (Ren, ¶ [0061], a number of such errors exceeding a threshold value, a number of errors exceeding a threshold value with a specified time period; each processing node has threshold value)
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Ren into the method of Jenkins to provide a method wherein the error threshold comprises a first error threshold, wherein if a second error threshold associated with the first processing element or the second processing element is reached, determining the first processing element or the second processing element to be faulty. The modification would be obvious because such information allows system to decide on when to declare the node is considered to be faulty (Ren, ¶ [0061]).
As per claim 9, the rejection of claim 1 is incorporated and Ren further teaches:
wherein each processing element of the three processing elements comprises a separate processor of a computing system or system-on-chip (SoC) (Ren, Fig. 4, ¶ [0024], ¶ [0044], CPU-GPU pairs running in lockstep, ¶ [0090], SOCs)
Claims 10, 11, 14-16 are method claims corresponding to the apparatus claims 1, 2, 5-7 respectively and are rejected for the same reasons set forth in connection of the rejections of claims 1, 2, 5-7 above.
Claims 17, 18 are machine-readable medium claims corresponding to the apparatus claims 1, 2 respectively and are rejected for the same reasons set forth in connection of the rejections of claims 1, 2 above, and Jenkins teaches a machine-readable medium (Jenkins, pg. 28, col. 1, Abstract, fault tolerant computers).
Claim Rejections - 35 USC § 103
Claim(s) 3, 4, 12, 13, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jenkins, Ren, and further in view of Selwan, Pierre (PG Pub. 2021/0,373,898 A1) [hereafter Selwan].
As per claim 3, the rejection of claim 1 is incorporated and Ren further teaches:
wherein the tracking circuitry is to responsively associate an additional error with the one processing element (Ren, ¶ [0061], a number of such errors exceeding a threshold value, a number of errors exceeding a threshold value with a specified time period)
Jenkins and Ren do not teach:
monitoring circuitry to monitor memory transactions performed by the three processing elements and to detect a difference in a memory transaction associated with any one processing element of the three processing elements;
However, Selwan in an analogous art teaches:
monitoring circuitry to monitor memory transactions performed by the three processing elements and to detect a difference in a memory transaction associated with any one processing element of the three processing elements; (Selwan, ¶ [0031-0032], determining the processors running lockstep mode are executing different instructions)
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Selwan into the combined method of Jenkins and Ren to provide monitoring circuitry to monitor memory transactions performed by the three processing elements and to detect a difference in a memory transaction associated with any one processing element of the three processing elements. The modification would be obvious because such determination allows a recovery operation to be performed (Selwan, ¶ [0031]).
As per claim 4, the rejection of claim 3 is incorporated and Selwan further teaches:
wherein the monitoring memory transactions comprises comparing addresses used to fetch instructions by each processing element and detecting when an address used to fetch an instruction by the one processing element is different from an address used to fetch instructions by the other two processing elements (Selwan, ¶ [0031], instruction fetch address mismatch)
Claims 12, 13 are method claims corresponding to the apparatus claims 3, 4 respectively and are rejected for the same reasons set forth in connection of the rejections of claims 3, 4 above.
Claims 19, 20 are machine-readable medium claims corresponding to the apparatus claims 3, 4 respectively and are rejected for the same reasons set forth in connection of the rejections of claims 3, 4 above.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jenkins, Ren, and further in view of Brown et al. (PG Pub. 2013/0,159,799 A1) [hereafter Brown].
As per claim 8, the rejection of claim 1 is incorporated:
Jenkins and Ren do not teach:
wherein each processing element of the three processing elements comprises a core of a processor of system-on-chip (SoC);
However, Brown in an analogous art teaches:
wherein each processing element of the three processing elements comprises a core of a processor of system-on-chip (SoC); (Brown, ¶ [0008], multi-core integrated circuit device of the type including a plurality of processing cores, ¶ [0064], SOC)
It would have been obvious to a person of ordinary skill of the art before the effective filing date of the invention to incorporate teachings of Brown into the combined method of Jenkins and Ren to provide an apparatus wherein each processing element of the three processing elements comprises a core of a processor of system-on-chip (SoC). The modification would be obvious because system comprising multiple processors are well-known hardware configuration that improves reliability while reducing cost.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PG Pub. 2024/0,095,133 A1 discloses a system capable of executing three or more cores to each execute identical instructions and activating an error detection mode that compares output data of different cores to determine if output data from different cores match.
PG Pub. 2023/0,291,405 A1 discusses triple modular redundancy with a voter circuit capable of detecting mismatches in the received signals from each of the processors and resetting the processor with the mismatch.
PG Pub. 2022/0,171,694 A1 discloses synchronization of multi-core systems by monitoring a plurality of debug trace data streams for a redundantly operating system including a corresponding plurality of cores performing a task in parallel.
See PTO-892 for other references not listed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAE M KO whose telephone number is (571)270-3886. The examiner can normally be reached M-F 9 am - 5 pm.
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/CHAE M KO/Primary Examiner, Art Unit 2114
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