DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1, Statutory Category: Yes, the claim 1 is a computer-implemented method that recites a series of steps and therefore falls in the statutory category of a process.
Step 2A- Prong 1: Judicial Exception Recited: Yes, the claim recites: “detecting that a host server that is connected to the DPU is unresponsive when the hardware watchdog timer expires without receiving a timer reset request from a host watchdog service timer thread running in the host server.” As drafted, the claim as a whole recites a method including step that could be performed in the human mind, but for the recitation of generic computing components. The human mind can easily judging/evaluating/determining/detecting whether the host server that is connected to the DPU is unresponsive or responsive by determining if the hardware watchdog timer expires without receiving a timer reset request from a host watchdog service timer thread running in the host server”. Therefore, but for the recitation of generic computing components, these steps may be a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion).
Therefore, yes, the claims do recite judicial exceptions.
Step 2A- Prong 2: Integrated into a practical Application: No, this judicial exception is not integrated into a practical application. In particular, the claim recites an additional limitations that “at a data processing unit (DPU), enabling a hardware watchdog timer in the DPU; and at the hardware watchdog timer in the DPU” which is directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they not impose any meaningful limits on practicing the abstract idea. Therefore, the claim is directed to the abstract idea.
Step 2B: Claim provides an Inventive Concept: No. The additional element “at a data processing unit (DPU), enabling a hardware watchdog timer in the DPU; and at the hardware watchdog timer in the DPU” which is directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). These additional elements and combination of the elements does not amount to significant more than the exception itself or provide an inventive concept in Step 2B.
For these reasons, there is no inventive concept in the claim, and thus the claim is ineligible.
Independent claims 10 and 19 are rejected for the same reason as claim 1 above. Claim 10 further recites “A non-transitory computer-readable storage medium containing program instructions, wherein execution of the program instructions by one or more processors causes the one or more processors to perform steps”. Claim 19 further recites “A system comprising: memory; and at least one processor configured to”. These additional elements are directed to generic computing components/functions (MPEP § 2106.05(b) merely applying the abstract idea (MPEP § 2106.05(f)).
With respect to the dependent claim 2, the claim elaborates that at the hardware watchdog timer running in the DPU, resetting the DPU after detecting that the host server that is connected to the DPU is unresponsive (“resetting” which is directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f)).
With respect to the dependent claim 3, the claim elaborates that at the hardware watchdog timer, transmitting an interrupt signal to the DPU after detecting that the host server that is connected to the DPU is unresponsive (“transmitting an interrupt signal” which is insignificant extra solution activity (i.e., transmitting data) See MPEP 2106.05(g)), and Courts have identified “receiving and transmitting data, storing and retrieving information”, et cetera as well understood, routine, conventional and mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
With respect to the dependent claim 4, the claim elaborates that at the DPU, transmitting a bootup completion indication signal to the host server to notify the host server that a bootup of the DPU is completed; and at the DPU, transmitting a watchdog capability information signal to the host server to notify the host server of capability information of the hardware watchdog timer in the DPU (“transmitting a bootup completion indication signal” and “transmitting a watchdog capability information signal” are insignificant extra solution activity (i.e., transmitting data) See MPEP 2106.05(g)), and Courts have identified “receiving and transmitting data, storing and retrieving information”, et cetera as well understood, routine, conventional and mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
With respect to the dependent claim 5, the claim elaborates that wherein enabling the hardware watchdog timer in the DPU comprises: at the DPU, receiving a watchdog enablement request signal from the host server; and upon receiving the watchdog enablement request signal, configuring a timeout period of the hardware watchdog timer in the DPU and enabling the hardware watchdog timer in the DPU (“receiving a watchdog enablement request signal” is insignificant pre-solution data gathering (see MPEP § 2106.05(g))) which are well understood, routine, conventional activity (see MPEP § 2106.05(d)). Courts have identified “receiving and transmitting data, storing and retrieving information”, et cetera as well understood, routine, conventional and mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). In addition, “configuring a timeout period” and “enabling the hardware watchdog timer” are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
With respect to the dependent claim 6, the claim elaborates that at the DPU, transmitting a watchdog enablement confirmation signal to the host server to inform the host server that the hardware watchdog timer in the DPU is enabled (“transmitting” is insignificant extra solution activity (i.e., transmitting data) See MPEP 2106.05(g)), and Courts have identified “receiving and transmitting data, storing and retrieving information”, et cetera as well understood, routine, conventional and mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
With respect to the dependent claim 7, the claim elaborates that wherein, in response to the watchdog enablement confirmation signal, a timeout period of a timeout timer of the host watchdog service timer thread is set and the host watchdog service timer thread is enabled (“a timeout period of a timeout timer of the host watchdog service timer thread is set and the host watchdog service timer thread is enabled” are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
With respect to the dependent claim 8, the claim elaborates that at the DPU, resetting the hardware watchdog timer in the DPU in response to the timer reset request from the host watchdog service timer thread, wherein the timer reset request is generated by the host watchdog service timer thread upon an expiration of the timeout timer of the host watchdog service timer thread (“resetting the hardware watchdog timer” is directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
With respect to the dependent claim 9, the claim elaborates that wherein the DPU is connected to the host server through a Peripheral Component Interconnect Express (PCIe) interface (“wherein the DPU is connected to the host server through a Peripheral Component Interconnect Express (PCIe) interface” are directed to generic computing components/functions (MPEP § 2106.05(b) merely applying the abstract idea (MPEP § 2106.05(f)).
Dependent claims 11-18 recite the same features as applied to claims 2-9 respectively above, therefore they are also rejected under the same rationale.
Dependent claim 20 recites the same features as applied to claim 2 above, therefore it is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10-11 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over MAITY et al. (US Pub. 2015/0149815 A1) in view of Suryawanshi (US Pub. 2010/0306518 A1) and further in view of Zhang et al. (US Pub. 2016/0378587 A1).
As per claim 1, MAITY teaches the invention substantially as claimed including A computer-implemented method comprising:
at a service processor, enabling a hardware watchdog timer in the service processor (MAITY, Fig. 1, 120 service processor, 182 watchdog module (as hardware watchdog timer is enabled); [0053] lines 1-4, As used herein, the term "module" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC); an electronic circuit; [0108] lines 3-4, the watchdog module 182 can be one or more timers); and
at the hardware watchdog timer in the service processor, detecting that a host server that is connected to the service processor is unresponsive when the hardware watchdog timer expires without receiving a timer reset request from a host process running in the host server (MAITY, Fig. 1, 110 host computer (as host server), BIOS 170; [0107] lines 1-17, the watchdog module 182 can be an electronic timer program with a predetermined period of time. The watchdog timer constantly receives notification signals from the host computer 110 to restart the watchdog timer (as timer reset request) in order to prevent the timer from elapsing or timing out. The act of restarting a watchdog timer of the watchdog module 182 is sometimes referred to as "kicking the dog," and the notification signal to restart the watchdog timer may be referred to as a "kick" signal. For example, during normal operation of the booting process, the BIOS 170 may regularly send kick signals to the SP 120 to restart the watchdog timer (as host process) of the watchdog module 182. If an error occurs during the booting process, the BIOS 170 stops processing with the follow-up booting procedures. Thus, the BIOS 170 will not continue sending the kick signal to the SP 120 to restart the watchdog timer of the watchdog module 182; also see [0111] lines 1-8, Upon receiving the kick signal within the predetermined period of time, the timer 186 of the watchdog module 182 restarts without sending out any timeout signals. When an error occurs during the booting process, the BIOS 170 stops processing, and the CPU 112 stops sending the kick signal to the SP 120, causing the timer 186 to elapse (as host server is unresponsive when the hardware watchdog timer expires without receiving a timer reset request)).
MAITY fail to specifically teach the service processor is data processing unit (DPU), and when enabling a hardware watchdog timer, it is in the DPU.
However, Suryawanshi teaches the service processor is data processing unit (DPU), and when enabling a hardware watchdog timer, it is in the DPU (Suryawanshi, Fig. 1, 12 data processor, 24 watchdog timer; [0014] lines 1-15, a watchdog reset of a data processor 12 (e.g., microprocessor or microcontroller) may be triggered by a watchdog timer 24, where the watchdog reset resets or restarts (e.g., or switches off and on) the data processor 12 or the data processor 12 and associated input/output hardware. For example, the watchdog timer 24 may be integrated into the data processor 12 or may comprise a separate hardware circuit. A data processor 12 may support a watchdog reset that is triggered in response to a software fault or hardware fault. For example, a software fault, a software malfunction, a hardware fault, or a hardware malfunction causes or results in the signal or appropriate code not being generated or sent to the watchdog timer 24 prior to timeout of the watchdog timer 24, which triggers the watchdog reset to occur).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY with Suryawanshi because Suryawanshi’s teaching of watchdog timer of the data processor would have provided MAITY’s system with the advantage and capability to allow the system to utilizing the watchdog timer in the data processor for detecting potential errors in order to improving the system reliability and efficiency.
MAITY and Suryawanshi fail to explicitly teach a host process is host watchdog service timer thread.
However, Zhang teaches a host process is host watchdog service timer thread (Zhang, [0024] lines 1-4, creating a real-time kernel thread on a system kernel side to periodically transmit a heartbeat message to a hardware watchdog; [0040] lines 1-4, creating a real-time kernel thread on a system kernel side so as to periodically transmit a heartbeat message to a hardware watchdog; please note: Host was taught by MAITY).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY and Suryawanshi with Zhang because Zhang’s teaching of creating real-time kernel thread for periodically transmitting a heartbeat message to a hardware watchdog would have provided MAITY and Suryawanshi’s system with the advantage and capability to allow the system to easily determining whether the system is either responsive or unresponsive in order to take subsequence correction action to improving the system performance and reliability.
As per claim 2, MAITY, Suryawanshi and Zhang teach the invention according to claim 1 above. MAITY teaches detecting that the host server that is connected to the DPU is unresponsive (MAITY, Fig. 1, 110 host computer (as host server), BIOS 170; [0107] lines 1-17, the watchdog module 182 can be an electronic timer program with a predetermined period of time. The watchdog timer constantly receives notification signals from the host computer 110 to restart the watchdog timer in order to prevent the timer from elapsing or timing out. The act of restarting a watchdog timer of the watchdog module 182 is sometimes referred to as "kicking the dog," and the notification signal to restart the watchdog timer may be referred to as a "kick" signal. For example, during normal operation of the booting process, the BIOS 170 may regularly send kick signals to the SP 120 to restart the watchdog timer (as host process) of the watchdog module 182. If an error occurs during the booting process, the BIOS 170 stops processing with the follow-up booting procedures. Thus, the BIOS 170 will not continue sending the kick signal to the SP 120 to restart the watchdog timer of the watchdog module 182). In addition, Suryawanshi teaches at the hardware watchdog timer running in the DPU, resetting the DPU after detecting (Suryawanshi, [0014] lines 1-14, a watchdog reset of a data processor 12 (e.g., microprocessor or microcontroller) may be triggered by a watchdog timer 24, where the watchdog reset resets or restarts (e.g., or switches off and on) the data processor 12 or the data processor 12 and associated input/output hardware. For example, the watchdog timer 24 may be integrated into the data processor 12 or may comprise a separate hardware circuit. A data processor 12 may support a watchdog reset that is triggered in response to a software fault or hardware fault. For example, a software fault, a software malfunction, a hardware fault, or a hardware malfunction causes or results in the signal or appropriate code not being generated or sent to the watchdog timer 24 prior to timeout of the watchdog timer 24, which triggers the watchdog reset to occur).
As per claims 10-11, they are non-transitory computer-readable storage medium claims of claims 1-2 respectively above. Therefore, they are rejected for the same reasons as claims 1-2 respectively above. In addition, MAITY further teaches A non-transitory computer-readable storage medium containing program instructions, wherein execution of the program instructions by one or more processors causes the one or more processors to perform steps comprising (MAITY, [0029] lines 1-4, Certain aspects of the present disclosure direct to a non-transitory computer readable medium storing computer executable codes. The codes, when executed at a processor of a service processor (SP), are configured to).
As per claims 19-20, they are system claims of claims 1-2 respectively above. Therefore, they are rejected for the same reasons as claims 1-2 respectively above. In addition, MAITY further teaches memory; and at least one processor configured to (MAITY, [0029] lines 1-4, Certain aspects of the present disclosure direct to a non-transitory computer readable medium storing computer executable codes. The codes, when executed at a processor of a service processor (SP), are configured to).
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over MAITY, Suryawanshi and Zhang, as applied to claims 1 and 10 respectively above, and further in view of KONA et al. (US Pub. 2018/0225168 A1).
As per claim 3, MAITY, Suryawanshi and Zhang teach the invention according to claim 1 above. MAITY teaches detecting that the host server that is connected to the service processor is unresponsive (MAITY, Fig. 1, 110 host computer (as host server), BIOS 170; [0107] lines 1-17, the watchdog module 182 can be an electronic timer program with a predetermined period of time. The watchdog timer constantly receives notification signals from the host computer 110 to restart the watchdog timer in order to prevent the timer from elapsing or timing out. The act of restarting a watchdog timer of the watchdog module 182 is sometimes referred to as "kicking the dog," and the notification signal to restart the watchdog timer may be referred to as a "kick" signal. For example, during normal operation of the booting process, the BIOS 170 may regularly send kick signals to the SP 120 to restart the watchdog timer (as host process) of the watchdog module 182. If an error occurs during the booting process, the BIOS 170 stops processing with the follow-up booting procedures. Thus, the BIOS 170 will not continue sending the kick signal to the SP 120 to restart the watchdog timer of the watchdog module 182).
In addition, Suryawanshi teaches service processor is DPU and at the hardware watchdog timer, transmitting a signal to the DPU after detecting (Suryawanshi, [0014] lines 1-14, a watchdog reset of a data processor 12 (e.g., microprocessor or microcontroller) may be triggered by a watchdog timer 24, where the watchdog reset resets or restarts (e.g., or switches off and on) the data processor 12 or the data processor 12 and associated input/output hardware. For example, the watchdog timer 24 may be integrated into the data processor 12 or may comprise a separate hardware circuit. A data processor 12 may support a watchdog reset that is triggered in response to a software fault or hardware fault. For example, a software fault, a software malfunction, a hardware fault, or a hardware malfunction causes or results in the signal or appropriate code not being generated or sent to the watchdog timer 24 prior to timeout of the watchdog timer 24, which triggers the watchdog reset to occur).
MAITY, Suryawanshi and Zhang fail to specifically teach transmitted signal is an interrupt signal.
However, KONA teaches the transmitted signal is an interrupt signal (KONA, Fig. 4, system unresponsive, watchdog timer fires; [0002] lines 10-12, The firing of the timer can cause an interrupt, which can be routed in order to cause the processing circuitry to be reset).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY, Suryawanshi and Zhang with KONA because KONA’s teaching of providing a watchdog timer to respective devices for sending the interrupt when determining that corresponding device is unresponsive would have provided MAITY, Suryawanshi and Zhang’s system with the advantage and capability to easily reset the corresponding devices based on the interrupt which improving the system performance and efficiency.
As per claim 12, it is a non-transitory computer-readable storage medium claim of claim 3 above. Therefore, it is rejected for the same reason as claim 3 above.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over MAITY, Suryawanshi and Zhang, as applied to claims 1 and 10 respectively above, and further in view of Benisty (US Patent. 10,860,333 B1) and TSUCHIYA (US Pub. 2017/0036557 A1).
As per claim 4, MAITY, Suryawanshi and Zhang teach the invention according to claim 1 above. Suryawanshi teaches at the DPU [for bootup] (Suryawanshi, [0002] lines 1-15, data processor may support a watchdog reset or watchdog timer reset that is triggered in response to a software fault or hardware fault…Thus, there is a need for an improved method for managing the reset of a data processor).
MAITY, Suryawanshi and Zhang fail to specifically teach at the DPU, transmitting a bootup completion indication signal to the host server to notify the host server that a bootup of the DPU is completed; and at the DPU, transmitting a watchdog capability information signal to the host server to notify the host server of capability information of the hardware watchdog timer in the DPU.
However, Benisty teaches at the DPU, transmitting a bootup completion indication signal to the host server to notify the host server that a bootup of the DPU is completed (Benisty, Col 1, lines 26-27, Once the reset operations are completed, the NVMe device is reinitialized; Col 2, lines 9-11, transmitting a reset complete signal to the host system upon completion of the set of front-end reset tasks; Col 5, lines 53-56, the NVMe device controller 105 will send a signal to the host that the reset is complete once the front-end 115 reset operations are complete; please note: DPU was taught by Suryawanshi).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY, Suryawanshi and Zhang with Benisty because Benisty’s teaching of send a reset complete signal to the host for indicating the reset is complete would have provided MAITY, Suryawanshi and Zhang’s system with the advantage and capability to allow the system to easily determining whether the reset is complete based on the received signal which improving the system performance and efficiency.
MAITY, Suryawanshi, Zhang and Benisty fail to specifically teach at the DPU, transmitting a watchdog capability information signal to the host server to notify the host server of capability information of the hardware watchdog timer in the DPU.
However, TSUCHIYA teaches at the DPU, transmitting a watchdog capability information signal to the host server to notify the host server of capability information of the hardware watchdog timer in the DPU (TSUCHIYA, [0077] lines 1-9, The household appliance A220 has the timer (As watchdog) by which the use time of the household appliance A220 can be set, so that the household appliance A220 is configured to start its operation when the use time set by the timer comes. The HEMS 260 continuously transmits the household appliances information and the vehicle information to the cloud server 30A. Further, when the timer is set in the household appliance A220, the HEMS 260 also transmits information about timer setting (as capability information) to the cloud server 30A; please note: DPU and watchdog were taught by Suryawanshi).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY, Suryawanshi, Zhang and Benisty with TSUCHIYA because TSUCHIYA’s teaching of transmitting the timer setting/capability information to the server would have provided MAITY, Suryawanshi, Zhang and Benisty’s system with the advantage and capability to allow the server to easily determining the time setting of the watchdog timer in order to allow the server to easily scheduling the different process based on the received timer setting which improving the system performance and efficiency.
As per claim 13, it is a non-transitory computer-readable storage medium claim of claim 4 above. Therefore, it is rejected for the same reason as claim 4 above.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over MAITY, Suryawanshi and Zhang, as applied to claims 1 and 10 respectively above, and further in view of Hata (US Pub. 2011/0119420 A1).
As per claim 5, MAITY, Suryawanshi and Zhang teach the invention according to claim 1 above. MAITY teaches enabling a hardware watchdog timer in the service processor (MAITY, Fig. 1, 120 service processor, 182 watchdog module (as hardware watchdog timer enabled); [0053] lines 1-4, As used herein, the term "module" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC); an electronic circuit; [0108] lines 3-4, the watchdog module 182 can be one or more timers). In addition, Suryawanshi teaches service processor is the DPU (Suryawanshi, [0002] lines 1-15, data processor may support a watchdog reset or watchdog timer reset that is triggered in response to a software fault or hardware fault…Thus, there is a need for an improved method for managing the reset of a data processor).
MAITY, Suryawanshi and Zhang fail to specifically teach wherein enabling the hardware watchdog timer in the DPU comprises: at the DPU, receiving a watchdog enablement request signal from the host server; and upon receiving the watchdog enablement request signal, configuring a timeout period of the hardware watchdog timer in the DPU and enabling the hardware watchdog timer in the DPU.
However, Hata teaches wherein enabling the hardware watchdog timer in the DPU comprises: at the DPU, receiving a watchdog enablement request signal from the host server, and upon receiving the watchdog enablement request signal, configuring a timeout period of the hardware watchdog timer in the DPU and enabling the hardware watchdog timer in the DPU (Hata, [0005] lines 3-15, a configuration in which a master control unit and a slave control unit are connected by a communication line, and a watchdog timer that monitors the operation of the CPU on the slave side is provided in the slave control unit. In this configuration, the master control unit (as host) issues an initialization command to the watchdog timer of the slave control unit at a prescribed interval (e.g., 100 ms) via the communication line (as receiving a watchdog enablement request signal from the host server), and loads an initial countdown value (e.g., 3 sec). A reset signal output from this watchdog timer is connected to a reset terminal of the CPU on the slave side, and the CPU on the slave side is reset when the countdown reaches zero without the initial value being loaded due to a system error or the like (as upon receiving the watchdog enablement request signal (i.e., initialization command), configuring a timeout period of the hardware watchdog timer in the DPU and enabling (i.e., loads an initial countdown value (e.g., 3 sec), and start counting); please note: host server was taught by MAITY and DPU was taught by Suryawanshi).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY, Suryawanshi and Zhang with Hata because Hata’s teaching of receiving an initialization command at the watchdog timer with setting the timeout value would have provided MAITY, Suryawanshi and Zhang’s system with the advantage and capability to allow the system to initializing the watchdog timer based on the initialization request and loading the timeout value based on that request in order to improving the system performance and efficiency.
As per claim 14, it is a non-transitory computer-readable storage medium claim of claim 5 above. Therefore, it is rejected for the same reason as claim 5 above.
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over MAITY, Suryawanshi and Zhang, as applied to claims 1 and 10 respectively above, and further in view of Weide et al. (US Pub. 2014/0229651 A1).
As per claim 6, MAITY, Suryawanshi and Zhang teach the invention according to claim 1 above. Suryawanshi teaches at the DPU (Suryawanshi, [0002] lines 1-15, data processor may support a watchdog reset or watchdog timer reset that is triggered in response to a software fault or hardware fault…Thus, there is a need for an improved method for managing the reset of a data processor).
MAITY, Suryawanshi and Zhang fail to specifically teach at the DPU, transmitting a watchdog enablement confirmation signal to the host server to inform the host server that the hardware watchdog timer in the DPU is enabled.
However, Weide teaches at the DPU, transmitting a watchdog enablement confirmation signal to the host server to inform the host server that the hardware watchdog timer in the DPU is enabled (Weide, Claim 15, process a connection request from an initiator for the first link rate; extract a timer from the connection request; determine whether the requested first link rate is available; start the timer when the link manager determines that the requested first link rate is unavailable; and issue a response to the host system to inform the host system that the timer has started and that connection at the requested first link rate is delayed while the timer is running (please note: DPU and watchdog timer was taught by Suryawanshi)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY, Suryawanshi and Zhang with Weide because Weide’s teaching of inform the host server that the timer is start/enabled would have provided MAITY, Suryawanshi and Zhang’s system with the advantage and capability to allow the system to easily determining when does the timer/watchdog is started in order to calculating the time associated with subsequence operations which improving the system performance and efficiency.
As per claim 7, MAITY, Suryawanshi, Zhang and Weide teach the invention according to claim 6 above. Weide teaches in response to watchdog enablement confirmation signal (Weide, Claim 15, start the timer when the link manager determines that the requested first link rate is unavailable; and issue a response to the host system to inform the host system that the timer has started and that connection at the requested first link rate is delayed while the timer is running). In addition, Zhang teaches a timeout period of a timeout timer of the host watchdog service timer thread is set and the host watchdog service timer thread is enabled (Zhang, [0024] lines 1-4, creating a real-time kernel thread on a system kernel side to periodically transmit a heartbeat message to a hardware watchdog; [0026] lines 5-7, in response to receiving a heartbeat message from a target process, reset a corresponding timer so as to retime a target process; [0039] lines 1-15, when the timing of the corresponding timer exceeds a predetermined time threshold, the target process is determined to be unresponsive, and a predetermined associated action is executed. According to embodiments of the present disclosure, a predetermined time threshold and a predetermined associated action may be set in response to a setting command from the target process. In an example embodiment, it may be continuously described based on an exemplary system architecture in a Linux operating system as shown in FIG. 1, that when a user space process invokes ioctl( ), a corresponding operation may be executed based on the specific command passed to ioctl( ), for example, obtaining a timeout value for a standard kernel timer, setting a timeout value, and setting an action associated with the timeout, etc; [0040] lines 1-4, creating a real-time kernel thread on a system kernel side so as to periodically transmit a heartbeat message to a hardware watchdog).
As per claim 15, it is a non-transitory computer-readable storage medium claim of claim 6 above. Therefore, it is rejected for the same reason as claim 6 above.
As per claim 16, it is a non-transitory computer-readable storage medium claim of claim 7 above. Therefore, it is rejected for the same reason as claim 7 above.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over MAITY, Suryawanshi, Zhang and Weide, as applied to claims 7 and 16 respectively above, and further in view of Soloway et al. (US Pub. 2021/0112137 A1).
As per claim 8, MAITY, Suryawanshi, Zhang and Weide teach the invention according to claim 7 above. Suryawanshi teaches at the DPU (Suryawanshi, [0002] lines 1-15, data processor may support a watchdog reset or watchdog timer reset that is triggered in response to a software fault or hardware fault…Thus, there is a need for an improved method for managing the reset of a data processor). In addition, Zhang teaches resetting the hardware watchdog timer in the DPU in response to the timer reset request from the host watchdog service timer thread, wherein the timer reset request is generated by the host watchdog service timer thread of the host watchdog service timer thread (Zhang, [0024] lines 1-4, creating a real-time kernel thread on a system kernel side to periodically transmit a heartbeat message to a hardware watchdog; [0026] lines 5-7, in response to receiving a heartbeat message from a target process, reset a corresponding timer so as to retime a target process; [0040] lines 1-4, creating a real-time kernel thread on a system kernel side so as to periodically transmit a heartbeat message to a hardware watchdog).
MAITY, Suryawanshi, Zhang and Weide fail to explicitly teach that the timer reset request is generated upon an expiration of the timeout timer.
However, Soloway teaches the timer reset request is generated upon an expiration of the timeout timer (Soloway, [0006] lines 1-6, the edge enabler server may initiate a watchdog timer upon registration of an edge application server for the UE, and the edge enabler client may initiate a keep-alive timer that has a shorter duration than the watchdog timer. Upon expiration of the keep-alive timer, the UE may transmit a keep-alive message to the edge enabler server, which triggers the edge enabler server to reset the watchdog timer).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY, Suryawanshi, Zhang and Weide with Soloway because Soloway’s teaching of the timer reset request is generated upon the timeout of the timer would have provided MAITY, Suryawanshi, Zhang and Weide’s system with the advantage and capability to allow the system to ensuring the watchdog has been reset on time in order to improving the system performance and efficiency.
As per claim 17, it is a non-transitory computer-readable storage medium claim of claim 8 above. Therefore, it is rejected for the same reason as claim 8 above.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over MAITY, Suryawanshi and Zhang, as applied to claims 1 and 10 respectively above, and further in view of Qin (US Pub. 2024/0273050 A1).
As per claim 9, MAITY, Suryawanshi and Zhang teach the invention according to claim 1 above. MAITY, Suryawanshi and Zhang fail to specifically teach wherein the DPU is connected to the host server through a Peripheral Component Interconnect Express (PCIe) interface.
However, Qin teaches wherein the DPU is connected to the host server through a Peripheral Component Interconnect Express (PCIe) interface (Qin, [0050] lines 6-9, the DPU 302 is connected to the host 301 through a peripheral component interconnect express (PCIe) interface (or is connected to a processor in the host through a PCIe bus)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of MAITY, Suryawanshi and Zhang with Qin because Qin’s teaching of DPU is connected to the host through a peripheral component interconnect express (PCIe) interface
would have provided MAITY, Suryawanshi and Zhang’s system with the advantage and capability to allow the system to increasing the data transmission speed between the DPU and the server in order to improving the system performance and efficiency.
As per claim 18, it is a non-transitory computer-readable storage medium claim of claim 9 above. Therefore, it is rejected for the same reason as claim 9 above.
Conclusion
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/ZUJIA XU/Examiner, Art Unit 2195