DETAILED ACTION
This Office Actions is in response to communication filed on 06/30/2023. Claims 1 – 20 are pending. Claim 1, 14, and 20 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 13-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty et al. US Pub. No. US 20170285940 A1 (hereafter Benisty), in further view of PARK et al. US Pub. No. US 20230087260 A1 (hereafter PARK).
Regarding claim 1, Benisty teaches the invention substantially as claimed: A computer-implemented method comprising: at a host server, allocating a plurality of log buffers; (e.g. FIG. 3 and [0036]: “The host 212 may include a host memory buffer (HMB) 300 and host buffers 301. The host buffers 301 may be a plurality of virtual memory locations that are originally allocated for a data transfer with the host as compared with the HMB 300 that is an intermediate storage for the data. The HMB 300 may be a part of the random access memory (RAM) (e.g. DRAM) of the host 212. The host memory buffer 300 may be a buffer that is allocated for usage by the device controller 102 that is distinct from the host buffers that are typically allocated for a data transfer. In other words, the device controller 102 accesses the host 212 memory. As further described below, the host memory buffer 300 may be used as a temporary storage of data to be transferred.”) The citation discloses the host memory buffers 300 and the host buffers/a plurality of log buffer, that are allocated for data transfer.
at the host server, receiving log data from a data processing unit (DPU) that is connected to the host server and storing the log data in the log buffers; (e.g. FIG. 3, [0035] FIG. 3 may be a portion of FIG. 1 or may illustrate an alternative embodiment. FIG. 3 illustrates an embodiment of the device controller 102, its internal block and their interactions. The host 212 sends commands to the device controller 102 using a physical interface which connects the host to the memory device controller 102. There are many protocols defined in the industry for this interface such as Peripheral Component Interconnect Express (PCIe),” and FIG. 7, [0036], [0050] FIG. 7 is a flow chart of the device controller operation. In particular, FIG. 7 illustrates the proposed NVMe device controller operation when executing a read command. Each read data is written to the HMB, read from the HMB and written again to the appropriate host buffer after the full data is accumulated in the HMB in order.”, [0051] - [0052]) The citations disclose at FIG. 3 and [0035] the device controller/DPU, that connected to the host using a physical interface (such as PCIe). At FIG. 7, [0050] – [0053], disclose the concept when the system performs the read commands, the read data is written/stored in the HMB, and then written again to the appropriate host buffer after full data is accumulated.
Benisty fails to teach and at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in storage of the DPU such that the host server is used to temporarily store the log data.
However, PARK teaches and at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in storage of the DPU such that the host server is used to temporarily store the log data. (e.g. FIG. 1 – FIG. 3, [0028]: “In accordance with an example embodiment of the present disclosure, the host device 100 may include a host controller 110 and a host device 120. The host memory 120 may serve as a buffer memory for temporarily storing data to be transmitted to the storage device 200 or data transmitted from the storage device 200.”) The citation discloses the concept of the host device 100 comprises host memory is used as a buffer memory for temporary storing data that to be transmitted to the storage device 200/DPU.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the and at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in storage of the DPU such that the host server is used to temporarily store the log data, as taught in PARK’s invention into Benisty’s invention because the addition features would help the system to improve reliability and data handling efficiency because the host server can quickly receive and hold the data before returning it to the storage, which helps reduce data loss, prevents storage bottlenecks at the storage, and supports smoother log management between the host server and the storage.
Regarding claim 2, Benisty, in view of PARK, discloses the computer-implemented method of claim 1, and Benisty further teaches wherein the storage of the DPU comprises a flash-based storage device. (e.g. FIG. 1A, and [0020]: “Non-volatile memory die 104 may include any suitable non-volatile storage medium, including NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable.”)
Regarding claim 3, Benisty, in view of PARK, discloses the computer-implemented method of claim 2, and PARK further teaches wherein the flash-based storage device comprises an embedded MultiMediaCard (eMMC). (e.g. [0030]: “the storage device 200 may be a device that complies with a universal flash storage (UFS) standard or an embedded multi-media card (eMMC) standard.”)
Regarding claim 13, Benisty, in view of PARK, discloses the computer-implemented method of claim 1, and Benisty further teaches wherein the DPU is connected to the host server through a Peripheral Component Interconnect Express (PCIe) interface. (e.g. FIG. 3 and [0035]: “FIG. 3 may be a portion of FIG. 1 or may illustrate an alternative embodiment. FIG. 3 illustrates an embodiment of the device controller 102, its internal block and their interactions. The host 212 sends commands to the device controller 102 using a physical interface which connects the host to the memory device controller 102. There are many protocols defined in the industry for this interface such as Peripheral Component Interconnect Express (PCIe), SATA and etc.”)
Regarding claim 14, it is a non-transitory computer-readable medium claim having similar limitations cited in claim 1, so it is also rejected under the same rational.
Regarding claim 15, it is a non-transitory computer-readable medium claim having similar limitations cited in claim 2, so it is also rejected under the same rational.
Regarding claim 16, it is a non-transitory computer-readable medium claim having similar limitations cited in claim 3, so it is also rejected under the same rational.
Regarding claim 20, it is a system claim having similar limitations cited in claim 1, so it is also rejected under the same rational.
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty, and PARK, in further view of Wibling et al. US Pub. No. US 20180232315 A1 (hereafter Wibling).
Regarding claim 4, Benisty, in view of PARK, discloses the computer-implemented method of claim 1, and Benisty further teaches wherein allocating the log buffers comprises: at the host server, allocating the log buffers to have a page size that is identical to the page size of the storage of the DPU. (e.g. [0051] In one exemplary embodiment, the data is transferred to and from the HMB. In block 702, the memory device controller initiates a data transfer phase of a read command. The read command may be received from the host. Based on the read command, memory space for the read command is allocated in the HMB in block 704. The allocated size for the HMB may be based on the total transfer size for the read command. Specifically, the allocated size for the HMB may be equal to the total transfer size for the read command.” and [0054]: “The device controller dynamically allocates HMB memory for each pending read command while the size of the allocated memory is equal to the size of the entire transfer size of the command. The HMB may used for storing every group/chunk of data associated with the command at the appropriate location so at the end of the process, the data will be stored in the HMB in order. When the data associated with the host read command is available in the allocated buffer, the device controller fetches the data from the HMB and writes it to the appropriate host buffers which have been allocated by the host using the SGL.”) The citation discloses the concept of allocation the HMB memory size at the host, wherein the HMB memory size is equal to the entire transfer size of the command from the storage device.
Benisty, in view of PARK fails to teach further comprising: at the host server, requesting a page size of the storage of the DPU from the DPU; and at the host server, receiving the page size of the storage of the DPU from the DPU,
However, Wibling teaches further comprising: at the host server, requesting a page size of the storage of the DPU from the DPU; and at the host server, receiving the page size of the storage of the DPU from the DPU (e.g. Claim 5: “The method of claim 3, further comprising: receiving a size request for the size of the shared memory region from the second application at the framework, the size request including the handle; and in response to the size request, returning the size of the shared memory region to the second application.”) The citation discloses the concept of requesting a size of a memory region/page size, and in response to the request, the system return the size of the requested memory region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the further comprising: at the host server, requesting a page size of the storage of the DPU from the DPU; and at the host server, receiving the page size of the storage of the DPU from the DPU, as taught in Wibling’s invention into Benisty and PARK’s invention because the addition features would help the system to the memory usage efficiency, lowers latency, and supports faster and more reliable storage operations between the host server and the storage.
Regarding claim 17, it is a non-transitory computer-readable medium claim having similar limitations cited in claim 4, so it is also rejected under the same rational.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty, and PARK, in further view of Shalev et al. US Pat. No. US 10917344 B2 (hereafter Shalev).
Regarding claim 5, Benisty, in view of PARK, discloses the computer-implemented method of claim 1, but fails to teach wherein allocating the log buffers comprises: allocating a plurality of virtual buffers in a software kernel of a virtual computing instance of the host server.
However, Shalev teaches wherein allocating the log buffers comprises: allocating a plurality of virtual buffers in a software kernel of a virtual computing instance of the host server. (e.g. FIG. 7B, 134 – Col 27, lines 43 – 55: “In some implementations, the virtual machine 752 may provide virtual memory 780, in which the user application 754 may allocate space for buffers 782. In these implementations, the addresses of the buffers 782 may be virtual, and reside in the virtual address space of the virtual machine 752. In many cases, the virtual addresses may be registered with the operating system kernel (either the virtual machine operating system or the host device operating system), and with a network adapter that is providing access to the network 730. Registration with the kernel may fix the mapping of the virtual addresses to guest physical addresses, which may prevent virtual pages that include the buffers 782 from being swapped out and creating some inefficiency.”) The citation discloses the allocating of the buffers 782 within the virtual memory of the VM, and the virtual addresses of the buffer are register with the OS kernel of the VM.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the wherein allocating the log buffers comprises: allocating a plurality of virtual buffers in a software kernel of a virtual computing instance of the host server, as taught in Shalev’s invention into Benisty and PARK’s invention because the addition features would allow the system to manage log data more flexibility and efficiently within a virtualized environment, and since the software kernel can allocate and manage memory resources for different virtual instances, which helps to improve scalability and resource control, isolate log handling operations, and support more reliable temporary storage of the log data.
Claims 6 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty and PARK, in further view of Smith et al. US Pub. No. US 20210084103 A1 (hereafter Smith).
Regarding claim 6, Benisty, in view of PARK, discloses the computer-implemented method of claim 1, but fails to teach wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting all of the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU.
However, Smith teaches wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting all of the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU. (e.g. FIG. 5 - 10, and [0112]: “Further, a migration may be performed in the background to gradually move all data from storage objects in the source cluster 400 to the destination cluster 500. For example, when the network is not busy, the storage driver 1050 may continue to read data from persistent disk 1012, and then write this data into persistent disk 1022. Once all the data are copied over, the persistent disk 1022 will contain the complete file system”) The citation discloses the concept where all of the data is moved from one source cluster to the destination cluster.
The teaching of Benisty, in view of PARK, discloses that the data is transmitted from log buffers back to the DPU, but does not clearly indicate that all data is transmitted. By combining the teaching of Smith about all data is transmitted, one with the ordinary skill in the art would be able to come up with the claim invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises:at the host server, transmitting all of the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU, as taught in Smith’s invention into Benisty and PARK’s invention because the addition features would allow the system to ensure that all data is returned to the DPU without leaving partial data at the host server, which improves data consistency and reliability, and reduces the risk of missing log information.
Claims 7, 8, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty and PARK, in further view of Russ US Pat. No. US 7234008 B1 (hereafter Russ).
Regarding claim 7, Benisty, in view of PARK, discloses the computer-implemented method of claim 1, but fails to teach wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on a ratio between a number of full log buffer or buffers in the log buffers and a number of empty log buffer or buffers of the log buffers.
However, Russ teaches wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on a ratio between a number of full log buffer or buffers in the log buffers and a number of empty log buffer or buffers of the log buffers. (e.g. FIG. 3 and 12 – Col 3, lines 33 – 45: “Generally, the present invention, in its simplest form, releases partially full buffers based on the number of empty buffers in a sender's buffer pool 306, 308. That is, in an embodiment of the present invention, partially full buffers may be released by a sender to a receiver whenever the number of empty buffers in a sender's buffer pool exceeds some type of predetermined threshold. Accordingly, it is preferable to provide both the CPU 302 and IOP 304 with their own buffer pool 308, 306, respectively. The buffer pools are preferably any fixed number of buffers wherein the buffers may be of any size, as desired. The buffers are preferably located in a memory wherein the CPU 302 and IOP 304 have read/write access.”) The citation discloses the buffer pool 306 and 308 that comprise empty buffers and full buffers, and the system compares the number of empty buffers against a threshold, where the number of empty buffers also relative to buffers that are currently occupied or in use within the buffer pool, in which also reflects a relationship between empty buffer and full buffer within the buffer pool. Although Russ does not clearly use the term “ratio”, Russ still evaluates the relative condition between full buffers and empty buffer, which is the same underlying concept of the relationship between the full buffers and empty buffer of the claim invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on a ratio between a number of full log buffer or buffers in the log buffers and a number of empty log buffer or buffers of the log buffers, as taught in Russ’s invention into Benisty and PARK’s invention because the addition features would enable the system to send data in a more balanced and adaptive way, which helps to avoid overload, and ensure smoother and more efficiency transferring data.
Regarding claim 8, Benisty, in view of PARK and Russ, discloses the computer-implemented method of claim 7, and Russ further teaches wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on the ratio between the number of the full log buffer or buffers in the log buffers and the number of the empty log buffer or buffers of the log buffers comprises:at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU when the ratio between the number of the full log buffer or buffers in the log buffers and the number of the empty log buffer or buffers of the log buffers exceeds a predetermined threshold. (e.g. FIG. 3 and 12 – Col 3, lines 33 – 45: “Generally, the present invention, in its simplest form, releases partially full buffers based on the number of empty buffers in a sender's buffer pool 306, 308. That is, in an embodiment of the present invention, partially full buffers may be released by a sender to a receiver whenever the number of empty buffers in a sender's buffer pool exceeds some type of predetermined threshold. Accordingly, it is preferable to provide both the CPU 302 and IOP 304 with their own buffer pool 308, 306, respectively. The buffer pools are preferably any fixed number of buffers wherein the buffers may be of any size, as desired. The buffers are preferably located in a memory wherein the CPU 302 and IOP 304 have read/write access.”) The citation discloses the buffer pool 306 and 308 that comprise empty buffers and full buffers, and the system compares the number of empty buffers against a predetermined threshold.
Regarding claim 18, it is a non-transitory computer-readable medium claim having similar limitations cited in claim 8, so it is also rejected under the same rational.
Claims 9, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty and PARK, in further view of WALSH et al. US Pub. No. US 20190324658 A1 (hereafter WALSH).
Regarding claim 9, Benisty, in view of PARK, discloses the computing system of claim 1, but fails to teach wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on a total number of full log buffers in the log buffers.
However, WALSH teaches wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on a total number of full log buffers in the log buffers. (e.g. [0045]: “Regarding operation 356 of method 300, the command processor may automatically send latency QoS status feedback to the host upon the occurrence of one or more predetermined conditions taking place. Such predetermined conditions may include, but are not limited to ........... a specific threshold of a number of write buffers full being exceeded; and/or a specific threshold of a number of read buffers full being exceeded.”) The citation discloses the concept of a threshold of read or write buffer full is exceeded. By combining with the teaching of Benisty, in view of PARK, that the action is sending data back to the DPU, one with the ordinary skill in the art would be able to come up with the claim invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on a total number of full log buffers in the log buffers, as taught in WALSH’s invention into Benisty and PARK’s invention because the addition features would improve the overall system resource management and reliability, because the host can prevent the buffer from becoming overload, reduce the risks of losing new data, and support more efficient of data transferring.
Regarding claim 10, Benisty, in view of PARK and WALSH, discloses the computer-implemented method of claim 7, and WALSH further teaches wherein transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU based on the total number of the full log buffers in the log buffers comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU when the total number of the full log buffers in the log buffers exceeds a predetermined threshold. (e.g. [0045]: “Regarding operation 356 of method 300, the command processor may automatically send latency QoS status feedback to the host upon the occurrence of one or more predetermined conditions taking place. Such predetermined conditions may include, but are not limited to ........... a specific threshold of a number of write buffers full being exceeded; and/or a specific threshold of a number of read buffers full being exceeded.”) The citation discloses the concept of a threshold of read or write buffer full is exceeded. By combining with the teaching of Benisty, in view of PARK, that the action is sending data back to the DPU, one with the ordinary skill in the art would be able to come up with the claim invention.
Regarding claim 19, it is a non-transitory computer-readable medium claim having similar limitations cited in claim 10, so it is also rejected under the same rational.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty and PARK, in further view of OTA et al. US Pub. No. US 20130311989 A1 (hereafter OTA).
Regarding claim 11, Benisty, in view of PARK, discloses the computing system of claim 1, but fails to teach further comprising receiving a notification of a failure of the DPU, wherein at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU in response to the notification of the failure of the DPU.
However, OTA teaches further comprising receiving a notification of a failure of the DPU, wherein at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU in response to the notification of the failure of the DPU. (e.g. [0111]: “Upon detection of a fault event, a fault notification is sent to event monitoring module of DRAS 160. The fault notification may relate to a failure on a storage system, host, or switch. The notification may include information related to the event and identification information for hardware associated with the failure, as shown in FIG. 9C.” and [0112 – 0113]) The citation discloses the concept when the system receives the fault notification relates to a failure on a storage system/notification of a failure of the DPU, the system performs some actions corresponding to the receiving fault notification. By combining with the teaching of Benisty, in view of PARK, that the action is sending data back to the DPU, one with the ordinary skill in the art would be able to come up with the claim invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the such that the further comprising receiving a notification of a failure of the DPU, wherein at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU in response to the notification of the failure of the DPU, as taught in OTA’s invention into Benisty and PARK’s invention because the newly added limitation would enable the system to make the determination that the storage device are insufficiently and unreliable to be utilized, which improves the stability, reduce unexpected behavior, and prevent the overall system from failure due to the failure of the storage device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty and PARK, in further view of Glimcher et al. US Pub. No. US 20240378132 A1.
Regarding claim 12, Benisty, in view of PARK, discloses the computing system of claim 1, but fails to teach further comprising at the host server, receiving a notification that a manual log collection is triggered at the DPU, wherein at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU in response to the notification that the manual log collection is triggered at the DPU.
However, Glimcher teaches further comprising at the host server, receiving a notification that a manual log collection is triggered at the DPU, wherein at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU in response to the notification that the manual log collection is triggered at the DPU. (e.g. FIG. 4 and [0036]: “As such, embodiments of decision block 410 may include the log collection engine 310 monitoring for a periodic log collection instruction that was previously configured to provide for the periodic log collections described above, a manual log collection instruction that may be received via the network 204 from a management system, and/or any other log collection instruction that would be apparent to one of skill in the art in possession of the present disclosure.”) The citation discloses the concept of collecting logs data, which comprise manual log collection. By combining with the teaching of Benisty, in view of PARK, that the action is sending data back to the DPU, with the teaching of Glimcher about the manual log collection, one with ordinary skills in the art would be able to come up with the claim invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the further comprising at the host server, receiving a notification that a manual log collection is triggered at the DPU, wherein at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU comprises: at the host server, transmitting the log data stored in the log buffers back to the DPU to be stored in the storage of the DPU in response to the notification that the manual log collection is triggered at the DPU, as taught in Glimcher’s invention into Benisty and PARK’s invention because the newly added limitation would improve efficiency and system control operation because the manual log collection process can gather complete set of logs, which helps provide better visibility into system events and reduces the chance of missing log data during system review.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20170123835 A1: a method of controlling a communication path among a plurality of virtual machines operating in one or more physical machines, the method includes allocating a virtual buffer serving as an alias of an actual buffer of a first virtual machine to a communication port that serves as a destination to which a communication path is changed from the first virtual machine and a second virtual machine directly or indirectly communicates with using a communication path change instruction as a trigger. Then, performing memory address translation on a region of the memory referred to by the virtual buffer, and generating the communication path between the first virtual machine and the second virtual machine by associating a region of the memory referred to by the first virtual machine and a region of the memory referred to by the second virtual machine.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs
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/TUAN M NGUYEN/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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