DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the America Invents Act (AIA ).
General Information Matter
Please note, the instant Non-Provisional application (18/217,484) under prosecution at the United States Patent and Trademark Office (USPTO) has been assigned to David Zarka (Examiner) in Art Unit 2449. To aid in correlating any papers for 18/217,484, all further correspondence regarding the instant application should be directed to the Examiner.
Joint Inventors
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 C.F.R. § 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential § 102(a)(2) prior art against the later invention.
Drawings
37 C.F.R. § 1.84(q) recites “Lead lines are required for each reference character except for those which indicate the surface or cross section on which they are placed.” Moreover, 37 C.F.R. § 1.84(r) recites “Arrows may be used at the ends of lines, provided that their meaning is clear, as follows: (1) On a lead line, a freestanding arrow to indicate the entire section towards which it points.”
Figure 22, item 2200 is a reference character that does not indicate a surface or cross section on which it is placed. Thus, the drawings are objected to under 37 C.F.R. § 1.84(q) for failing to include lead lines for each reference character. Moreover, Figure 22, item 2200 appears to indicate the entire section towards which it points. Thus, the Examiner recommends adding to arrow at the end of the lead line.
Figure 27, item 2700; Figure 27B, item 2750 by analogy.
37 C.F.R. § 1.84(q) recites “[Lead lines] must originate in the immediate proximity of the reference character and extend to the feature indicated.”
The drawings are objected to under 37 C.F.R. § 1.84(q) for failing to extend lead lines to the feature indicated. See Figure 13(B), item 1390.
Corrected drawing sheets in compliance with 37 C.F.R. § 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Applicants are advised to employ the services of a competent patent draftsperson outside the Office, as the USPTO does not prepare new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 C.F.R. § 1.121(d). If the changes are not accepted by the Examiner, Applicants will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy Specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicants’ cooperation is requested in correcting any errors of which Applicants may become aware in the Specification.
Claim Objections
The following is a quotation of 37 C.F.R. § 1.71(a):
The specification must include a written description of the invention or discovery and of the manner and process of making and using the same, and is required to be in such full, clear, concise, and exact terms as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same.
Claims 5 and 15 are objected to under 37 C.F.R. § 1.71(a) for the following informalities:
Claim 5, line 5 should be “only if the MCU matches.”
Claim 15, line 5 by analogy.1
Means-plus-Function Language
The following is a quotation of 35 U.S.C. § 112(f):
ELEMENT IN CLAIM FOR A COMBINATION.—An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof
The claims in the instant application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the Specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the Specification when 35 U.S.C. § 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. § 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. § 112(f). The presumption that § 112(f) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function.
Absence of the word “means” (or “step for”) in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. § 112(f). The presumption that § 112(f) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function.
Claim elements in the instant application that use the word “means” (or “step for”) are presumed to invoke 35 U.S.C. § 112(f) except as otherwise indicated in an Office action. Similarly, claim elements that do not use the word “means” (or “step for”) are presumed not to invoke § 112(f) except as otherwise indicated in an Office action.
The instant application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. § 112(f) because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations2 are:
“security unit” (claim 3, line 3; claim 13, line 3; claim 19, line 4); and
“secure interface unit” (claim 3, line 2).
Since the claim limitations invoke 35 U.S.C. § 112(f), claims 3, 4, 13, 14, 19, and 20 have been interpreted to cover the corresponding structure described in the Specification that achieves the claimed function, and equivalents thereof.
With respect to the claimed function corresponding to the “security unit” (claim 3, line 3; claim 13, line 3; claim 19, line 4), the Specification discloses security units residing with dies to achieve the claimed function. See Spec. ¶¶ 219–221; Figure 30.
If Applicants do not intend to have the claim limitations treated under 35 U.S.C. § 112(f), Applicants may amend the claims so that they will clearly not invoke § 112(f), or present a sufficient showing that the claims recite sufficient structure, material, or acts for performing the claimed function to preclude application of § 112(f).
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011) (available at https://www.govinfo.gov/content/pkg/FR-2011-02-09/pdf/2011-2841.pdf).
Claim Rejections – 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. § 112(b): “The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.”
The MPEP recites “[d]uring examination, after applying the broadest reasonable interpretation consistent with the specification to the claim, if the metes and bounds of the claimed invention are not clear, the claim is indefinite and should be rejected.” MPEP § 2173.02(I) (citing In re Packard, 751 F.3d 1307, 1311 (Fed. Cir. 2014)). “For example, if the language of a claim, given its broadest reasonable interpretation, is such that a person of ordinary skill in the relevant art would read it with more than one reasonable interpretation, then a rejection under 35 U.S.C. 112(b) . . . is appropriate.” Id. See also id. § 2173.05(e)(discussing indefiniteness arising for terms lacking proper antecedent basis).
Claims 3 and 4 are rejected under § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As discussed above, claim element “secure interface unit” (claim 3, line 2) is a limitation that invokes 35 U.S.C. § 112(f). The Specification is devoid of adequate structure to perform the claimed function. In particular, the Specification states the claimed function of establishing secure communication between host software and at least one security unit is performed by a “secure interface unit.” See Spec. ¶ 240. There is no disclosure of any particular structure, either explicitly, implicitly, or inherently, to establish the secure communication. The use of the term “secure interface unit” is not adequate structure for establishing the secure communication because it does not describe a particular structure for performing the function. As would be recognized by those of ordinary skill in the art, establishing a secure communication can be performed in any number of ways in hardware, software or a combination of the two. The Specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function.
The written description, therefore, fails to clearly link or associate the disclosed structure, material, or acts to the claimed function such that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function. Accordingly, the claim is indefinite and is rejected under 35 U.S.C. § 112(b).
Applicants may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. § 112(f); or
(b) Amend the written description of the Specification such that it clearly links or associates the corresponding structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. § 132(a)); or
(c) State on the record where the corresponding structure, material, or acts are set forth in the written description of the Specification and linked or associated to the claimed function. For more information, see 37 CFR § 1.175(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections – 35 U.S.C. § 101
The following is a quotation of 35 U.S.C. § 101: “Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.”
MPEP § 2106.03(II) recites:
[T]he [broadest reasonable interpretation (BRI)] of machine readable media can encompass non-statutory transitory forms of signal transmission, such as a propagating electrical or electromagnetic signal per se. See In re Nuijten, 500 F.3d 1346, 84 USPQ2d 1495 (Fed. Cir. 2007). When the BRI encompasses transitory forms of signal transmission, a rejection under 35 U.S.C. 101 as failing to claim statutory subject matter would be appropriate. Thus, a claim to a computer readable medium that can be a compact disc or a carrier wave covers a non-statutory embodiment and therefore should be rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. See, e.g., Mentor Graphics v. EVE-USA, Inc., 851 F.3d at 1294-95, 112 USPQ2d at 1134 (claims to a “machine-readable medium” were non-statutory, because their scope encompassed both statutory random-access memory and non-statutory carrier waves).
Claims 17–20 are rejected under 35 U.S.C.§ 101 because the claimed invention is directed to nonstatutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to a “machine-readable medium.” Claim 17, line 1. The broadest reasonable interpretation of such a medium can encompass non-statutory transitory forms of signal transmission, such as a propagating electrical or electromagnetic signal per se.
The Examiner notes the Specification does not define a “machine-readable medium” to be a non-transitory machine-readable medium. Although paragraph 235 of the Specification discloses “[s]uch machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device,” the Examiner notes the disclosure is directed to a “machine-readable storage media” which is not recited in claim 17. And even assuming claim 17 recites a “machine-readable storage media,” paragraph 235 of the Specification discloses such a media “may” include non-transitory embodiments which is merely exemplary. The Examiner additionally notes other sections from the Specification that discuss non-transitory embodiments are also merely exemplary. See Spec. ¶¶ 43, 44, 85, 120, 258.
The Examiner suggests amending claim 17, line 1 to include a “non-transitory machine-readable medium.”
Claim Rejections – 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Shanmugam and Brewer
Claims 1, 5, 6, 11, and 15–17 are rejected under 35 U.S.C. § 103 as being obvious over Shanmugam et al. (US 2021/0240468 A1; filed Jan. 31, 2020) in view of Brewer (US 2020/0135720 A1; filed Sept. 5, 2019).
Regarding claim 1, while Shanmugam teaches a processor (“the chassis 202 may house a processing system (not illustrated, but which may include the processor 102 discussed above with reference to FIG. 1)” at ¶ 16) comprising:
a main memory (fig. 4, item 208) to store a corresponding microcode update (MCU) (fig. 4C, item 404b; intended use in italics);
a plurality of MCU staging memories (fig. 2, item 206b; “data regions” at ¶ 24), each MCU staging memory to temporarily store one or more of the MCUs (fig. 3, item 302; fig. 4A, item 400b; “perform write operations 400b to write the microcode update to the data region 206b in the memory device(s) 206” at ¶ 21) for one or more corresponding functional blocks of the plurality of functional blocks (intended use in italics); and
authentication hardware logic (figs. 4A, 4C; ¶¶ 21–22, 31) to attempt to validate (fig. 3, item 312; “the method 300 proceeds to decision block 312 where it is determined whether the microcode update is valid” at ¶ 30) each MCU of the one or more MCUs stored in each MCU staging memory, wherein each MCU is to be copied to a main memory (fig. 4C, item 208) only after a successful authentication (“in response to determining that the microcode update stored in the data region 206b provided by the memory device(s) 206 is valid, the microcode update engine 204 may operate to perform microcode update operations that include copying the microcode update from the data region 206b provided by the memory device(s) 206 to the main memory system 208” at ¶ 31),
Shanmugam does not teach (A) the main memory being non-volatile memory; (B) a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including the non-volatile memory; and (C) copying each MCU to a non-volatile memory of a corresponding functional block.
Brewer teaches non-volatile memory (“non-volatile memory partition” at ¶¶ 51, 119, 120);
a plurality of functional blocks (fig. 9, items 810–814, 910–924), each functional block operable, at least in part, based on microcode (“method 700 in general can be performed by processing logic that can include hardware (e.g., . . . microcode” at ¶ 70) and including the non-volatile memory (fig. 9, items 102, 104, 108);
and copying data to a non-volatile memory (fig. 9, items 102, 104, 108) of a corresponding functional block (fig. 9, items 810–814, 910–924).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention for Shanmugam’s main memory to be non-volatile memory, for Shanmugam to include a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including the non-volatile memory, and for Shanmugam’s copying of each MCU to be to a non-volatile memory of a corresponding functional block as taught by Brewer to “provide a better overall performance in implementing selected functions.” Brewer ¶ 70. Moreover, “to achieve performance improvements at reduced power.” Id. ¶ 21.
Regarding claim 5, while Shanmugam teaches wherein to validate each MCU of the one or more MCUs stored in the MCU staging memory (fig. 3, item 312), the authentication hardware logic is to compare the MCU to an original MCU (fig. 3, item 306; ¶ 27) or a manifest associated with the original MCU and is to cause the MCU to be copied to the main memory of the corresponding functional block only of the MCU matches the original MCU (¶ 27) or is consistent with the manifest,
Shanmugam does not teach the main memory being non-volatile memory.
Brewer teaches non-volatile memory (“non-volatile memory partition” at ¶¶ 51, 119, 120).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention for Shanmugam’s main memory to be non-volatile memory as taught by Brewer to “provide a better overall performance in implementing selected functions.” Brewer ¶ 70. Moreover, “to achieve performance improvements at reduced power.” Id. ¶ 21.
Regarding claim 6, Shanmugam teaches further comprising:
execution circuitry to execute an MCU activation instruction (fig. 3, items 304–308) once each MCU is stored in a corresponding MCU staging memory (fig. 3, item 302; fig. 4A, item 400b; “perform write operations 400b to write the microcode update to the data region 206b in the memory device(s) 206” at ¶ 21), the authentication hardware logic to attempt to validate each MCU (fig. 3, item 312) responsive to the MCU activation instruction.
Regarding claim 11, while Shanmugam teaches a method (fig. 3, item 300) comprising:
temporarily storing one or more MCUs (fig. 3, item 302; fig. 4A, item 400b; “perform write operations 400b to write the microcode update to the data region 206b in the memory device(s) 206” at ¶ 21) in a corresponding MCU staging memory of a plurality of MCU staging memories (fig. 2, item 206b; “microcode updates may vary and may be written to data regions” at ¶ 24),
including a main memory (fig. 4, item 208) to store a corresponding microcode update (MCU) (intended use in italics);
attempting to validate (fig. 3, item 312; “the method 300 proceeds to decision block 312 where it is determined whether the microcode update is valid” at ¶ 30) each MCU of the one or more MCUs stored in each MCU staging memory; and
copying each MCU to a corresponding main memory (fig. 4C, item 208) of a corresponding functional block only after a successful authentication (“in response to determining that the microcode update stored in the data region 206b provided by the memory device(s) 206 is valid, the microcode update engine 204 may operate to perform microcode update operations that include copying the microcode update from the data region 206b provided by the memory device(s) 206 to the main memory system 208” at ¶ 31),
Shanmugam does not teach (A) the main memory being non-volatile memory; (B) the temporary storing of the one or more MCUs being for one or more corresponding functional blocks of a plurality of functional blocks of a processor; and (C) each functional block operable, at least in part, based on microcode and including the non-volatile memory.
Brewer teaches non-volatile memory (“non-volatile memory partition” at ¶¶ 51, 119, 120);
a storing of data (fig. 10; ¶¶ 119–120) being for one or more corresponding functional blocks of a plurality of functional blocks (fig. 9, items 810–814, 910–924) of a processor (“Each functional block of the array of functional blocks of 3D SIC 800 (functional block 810, 812, 814, 910, 912, 914, 920, 922, or 924) can include a respective processing logic partition including a processing core of a manycore processor.” at ¶ 112); and
each functional block (fig. 9, items 810–814, 910–924) operable, at least in part, based on microcode (“method 700 in general can be performed by processing logic that can include hardware (e.g., . . . microcode” at ¶ 70) and including the non-volatile memory (fig. 9, items 102, 104, 108).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention for Shanmugam’s main memory to be non-volatile memory, for Shanmugam’s temporary storing of the one or more MCUs to be for one or more corresponding functional blocks of a plurality of functional blocks of a processor, wherein each functional block is operable, at least in part, based on microcode and including the non-volatile memory as taught by Brewer to “provide a better overall performance in implementing selected functions.” Brewer ¶ 70. Moreover, “to achieve performance improvements at reduced power.” Id. ¶ 21.
Regarding claims 15 and 16, claims 5 and 6, respectively, recite substantially similar features. Thus, references/arguments equivalent to those present for claims 5 and 6 are equally applicable to, respectively, claims 15 and 16.
Regarding claim 17, Shanmugam teaches a machine-readable medium (fig. 1, item 114) having program code stored thereon which, when executed by a machine (fig. 1, item 100), is to cause the machine to perform operations according to claim 1. Thus, references/arguments equivalent to those present for claim 1 are equally applicable to claim 17.
Henry and Brewer
Claims 1, 11, and 17 are rejected under 35 U.S.C. § 103 as being obvious over Henry et al. (US 2010/0180104 A1; filed Mar. 13, 2009) in view of Brewer.
Regarding claim 1, while Henry teaches a processor (fig. 2, item 204) comprising:
a plurality of functional blocks (fig. 2, items 112, 114, 116, 118, 122, 202), each functional block operable, at least in part, based on microcode (¶¶ 3–4) and including a memory (fig. 2, item 114) to store a corresponding microcode update (MCU) (fig. 2, item 108; intended use in italics);
a plurality of MCU staging memories (fig. 2, item 202), each MCU staging memory to temporarily store one or more of the MCUs (fig. 6, item 606; ¶ 41) for one or more corresponding functional blocks of the plurality of functional blocks (intended use in italics); and
authentication hardware logic (¶¶ 15, 46) to attempt to validate (fig. 6, item 612) each MCU of the one or more MCUs stored in each MCU staging memory, wherein each MCU is to be copied (fig. 6, item 614) to a memory of a corresponding functional block (fig. 2, item 114) only after a successful authentication (Yes to fig. 6, item 612),
Henry does not teach the memory being non-volatile memory.
Brewer teaches non-volatile memory (“non-volatile memory partition” at ¶¶ 51, 119, 120).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention for Henry’s memory to be non-volatile memory as taught by Brewer to “provide a better overall performance in implementing selected functions.” Brewer ¶ 70. Moreover, “to achieve performance improvements at reduced power.” Id. ¶ 21.
Regarding claim 11, while Henry teaches a method comprising:
temporarily storing one or more MCUs (fig. 2, item 108) for one or more corresponding functional blocks (fig. 2, item 114) of a plurality of functional blocks (fig. 2, items 112, 114, 116, 118, 122, 202) of a processor (fig. 2, item 204) in a corresponding MCU staging memory (fig. 2, item 202) of a plurality of MCU staging memories (item 202 for each item 204), each functional block operable, at least in part, based on microcode (¶¶ 3–4) and including a memory (fig. 2, item 114) to store a corresponding microcode update (MCU) (fig. 2, item 108; intended use in italics);
attempting to validate (fig. 6, item 612) each MCU of the one or more MCUs stored in each MCU staging memory; and
copying each MCU to a corresponding memory of a corresponding functional block (fig. 2, item 114) only after a successful authentication (fig. 6, item 614),
Henry does not teach the memory being non-volatile memory.
Brewer teaches non-volatile memory (“non-volatile memory partition” at ¶¶ 51, 119, 120).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention for Henry’s memory to be non-volatile memory as taught by Brewer to “provide a better overall performance in implementing selected functions.” Brewer ¶ 70. Moreover, “to achieve performance improvements at reduced power.” Id. ¶ 21.
Regarding claim 17, Henry teaches a machine-readable medium (fig. 2, items 106, 112, 116, 202) having program code stored thereon which, when executed by a machine (fig. 2, item 200), is to cause the machine to perform operations according to claim 1. Thus, references/arguments equivalent to those present for claim 1 are equally applicable to claim 17.
Allowable Subject Matter
Claims 3 and 4 would be allowable if rewritten to (1) overcome the rejection under 35 U.S.C. § 112(b) set forth in this Office action; and (2) include all of the limitations of the base claim and any intervening claims.
Claims 2, 7–10, 12–14, and 18–20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure: US-20210326135-A1; US-20230097693-A1; US-20230034837-A1; US-20210365559-A1; US-20160180099-A1; US-20030196096-A1; and Microcode Update Guidance, INTEL, pp. 1–5 (June 2020).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to DAVID P. ZARKA whose telephone number is (703) 756-5746. The Examiner can normally be reached Monday–Friday from 9:30AM–6PM ET.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Vivek Srivastava, can be reached at (571) 272-7304. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicants are encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
/DAVID P ZARKA/PATENT EXAMINER, Art Unit 2449
1 The Examiner notes paragraphs 242 and 252 of the Specification disclose the same typographical error.
2 The Examiner notes “Applicants are free to invoke § 112 ¶ 6 for a claim term nested in a method claim. We have never held otherwise.” Rain Computing, Inc. v. Samsung Elecs. Am. Inc., 989 F.3d 1002, 1006 (Fed. Cir. 2021). See also Media Rights Technologies, Inc. v. Capital One Financial Corp., 800 F.3d 1366, 1374 (Fed. Cir. 2015) (holding that the term “compliance mechanism” in a method claim was a means-plus-function term); see also MPEP § 2181.
Prosecution Insights