DETAILED ACTION
This action is in response to the filing 06/30/2023. Claims 1-20 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 17-20 are rejected under 35 U.S.C. 101.
Claims 1-2, 5, 8-10, 13, and 16-18 are rejected under 35 U.S.C. 103.
Claims 3-4, 6-7, 11-12, and 14-15 contain allowable subject matter but are objected to as being dependent upon a rejected base claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 17 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of Claim 15’s recitation of “machine-readable medium having program code stored thereon” recites a transitory signal. A transitory signal, while physical and real, does not possess concrete structure that would qualify as a device or part under the definition of a machine, is not a tangible article or commodity under the definition of a manufacture (even though it is man-made and physical in that it exists in the real world and has tangible causes and effects), and is not composed of matter such that it would qualify as a composition of matter, see MPEP 2106.03. Claims 18-20 are dependent on Claim 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 8-10, 13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Habusha et al. (U.S. Patent No. 10067847) in view of Merten et al. (U.S. PGPub No. 20170371769), further in view of Rentschler et al. (U.S. PGPub No. 20120144240).
Regarding Claim 1, and similarly Claims 9 and 17, Habusha teaches [in bold],
A processor, comprising: a plurality of processing cores … (see CPUs (102) and CPU cores (804) [Fig. 1 & Fig. 8]; also see a computer readable media storing data and instructions [Col. 13, lines 43-64]);
processor trace circuitry to perform trace operations to capture and process information related to program code executed by one or more of the logical processors ("Each CPU core 804 may include an embedded trace module (ETM) and a PMU 802 that communicate with an on-chip tracing circuit 822 [processor trace circuitry]. Each performance monitoring unit may export a set of counter increment events or other events to be traced out" [Col. 11, line 64- Col. 12, line 1]; CPU executed code with corresponding timestamp and hardware event ("performance data") may be traced-out using the PMUs [Col. 11, lines 32-34]);
a performance monitoring unit (PMU) comprising a plurality of counter registers, the PMU to collect performance data related to execution of the program code ("Each CPU PMU may provide an array of counter units" [Col. 5, line 48]; CPU executed code with corresponding timestamp and hardware event ("performance data") may be traced-out using the PMUs [Col. 11, lines 32-34];
While Habusha discloses a debugger (106) in conjunction with configuration channel (120) [Fig. 1], Habusha does not appear to explicitly disclose and Merten teaches,
… configurable as a plurality of logical processors (in a system for performing event-based sampling based on every nth count of an event programmed into a performance monitoring counter [0018], the cores may support multithreading (where each core provides a logical core) [0102] where the cores provide virtual machines [0033])
a debug unit to perform debug operations and collect debug data related to execution of the program code (a debugger may receive a record packet [0055], the record packet including latency information, address information, transaction synchronization information, etc. ("debug data") [0050]);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the tracing and performance monitoring system of CPU cores as disclosed by Habusha to include cores configurable as logical processors and a debugger that receives debug data as disclosed by Merten. The resulting combination allows for a system that has the benefits of virtualization to be monitored, those benefits including simultaneous virtual systems protected from one another allowing for improved security of a guest OS [0022]. Further, a debugger receiving debug data allows for debugging with detailed contextual information to allow for identification of performance issues thus better formulating code [0021].
While Habusha discloses that the PMU’s counter unit may perform self-triggering [Col. 6, lines 20-25] and that tracing out may be triggered by the status of the trigger registers [Col. 11, lines 42-45] where the counter unit possesses control registers [Col. 6, lines 19-20 and 25-26], Habusha does not appear to explicitly disclose and Rentschler teaches,
and a plurality of trigger units, each trigger unit associated with a logical processor of the plurality of logical processors (see DSM (114) (“trigger units”) corresponding to both core 0 and core 1 core units (112) [Fig. 1]; where DSM is a debug state machine that allows for programming complex trigger sequences [0004])
and configured to communicate trigger event data to the processor trace circuitry in response to trigger events received from at least one of the debug unit and the PMU (see input signals DebugCrossTrigger and external triggers [Fig. 2 and Fig. 3]; status and control registers control the way the DSM triggers map to actions [0023, 0043]; further see pre-selected actions Trace_store_start and Trace_store_stop of Table 11 [Pg. 5]; where TraceStore is an outgoing action [Fig. 3])
in accordance with values of configuration bits in a corresponding trigger unit configuration register (status and control registers control the way the DSM triggers map to actions [0023, 0043] where the DSM is programmed to specify "MAIN CONTROL" and "PRE-SELECT ACTIONS" [0026, Fig. 3]; the trace data storage is controlled by a StoreToL2 bit in the dsm_control_status register, where storage is performed when the register is set and may be controlled by the trace start and trace stop actions from the DSM [0074]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the tracing and performance monitoring system that counts events and performs triggering based on the counted events of Habusha in view of Merten to include the DSM as a triggering unit of Rentschler. The resulting combination enables complex triggering sequences which allows for flexible and efficient debug visibility [Rentschler; 0014].
Regarding Claim 2, and similarly Claims 10 and 18, Habusha does not appear to disclose and Rentschler teaches,
The processor of claim 1 wherein the configuration bits comprise a plurality of trigger input selection bits to indicate the trigger events for which a trigger action is to be performed and a plurality of trigger action bits to indicate actions to be performed in response to the corresponding trigger events (status and control registers control the way the DSM triggers map to actions [0023, 0043]; see the example of [0043] describing PerfMon0 (incoming trigger, Fig. 3) prompts generation of chip_stopclk action (outgoing action, Fig. 3); the status and control registers possess corresponding bits to indicate events for which a particular triggered action may be performed [Pg. 6-7, Table 12]; also see bit action signals [0029]).
The same motivation for Claim 1 also applies to Claim 2.
Regarding Claim 5, and similarly Claim 13, Habusha does not appear to disclose and Rentschler teaches,
The processor of claim 2 wherein upon receipt of a first trigger event, the trigger unit is to transmit a message to the processor trace circuitry indicating a trace pause action or a trace resume action based on a value of one or more of the plurality of trigger action bits, wherein the processor trace circuitry is to responsively pause or resume the trace operations (status and control registers control the way the DSM triggers map to actions [0023, 0043] where the DSM is programmed to specify "MAIN CONTROL" and "PRE-SELECT ACTIONS" [0026, Fig. 3]; the trace data storage is controlled by a StoreToL2 bit in the dsm_control_status register, where storage is performed when the register is set and may be controlled by the trace start and trace stop actions from the DSM [0074]; where the Examiner notes a trace start action as being a "resume" action and a trace stop action as being a "pause" action; the processor may include a cache, where actions performed by the DSM include start or stop storing information to the cache ("transmit a message") [0015, also see (cache) L2 of the comments corresponding to Trace_store_stop and Trace_store_start] ).
The same motivation for Claims 1/2 also applies to Claim 5.
Regarding Claim 8 and similarly Claim 16, Habusha teaches,
The processor of claim 1 further comprising: a plurality of PMU configuration registers, each PMU configuration register associated with a counter register of the plurality of counter registers (where the counter unit may be enabled by setting a counter enable bit in a counter control register and the event to be monitored can be selected using a counter control register [Col. 6, lines 19-20 and 25-26])
and configured to store a bit value to indicate whether performance monitoring events associated with the corresponding counter register are to cause a trigger event to be transmitted to the trigger unit (where the event counter is programmed with a low threshold, high threshold, or granule for performing comparison to the count value in determining whether to generate an interrupt and/or trigger signal [Col. 4, lines 14-19]).
Allowable Subject Matter
Claims 3-4, 6-7, 11-12, and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s statement of reasons for indicating allowable subject matter:
Regarding Claim 3, and similarly Claim 11, while Habusha discloses that each PMU corresponds to each functional block, this information is not stored or associated. Therefore, the prior art of record fails to disclose, wherein the trigger unit is to associate attribution information indicating a particular intellectual property (IP) block, functional unit, or set of functional units with particular types of trigger events. Claims 4 and 12 depend on the allowable subject matter of Claims 3 and 11, respectively.
Regarding Claim 6, and similarly Claim 14, while Merten discloses a debugger that receives the record packet and interleaved trace data packets [0055] and that a base address and range for precise event-based sampling records may be defined by a register [0044], it is not disclosed that the debugger has this register or that the debugger indicates which registers are to cause a trigger event. The prior art of record fails to disclose, the debug unit further comprises: a plurality of debug registers, each debug register to store an address associated with debug operations; and a debug control register to store a plurality of bit values indicating which debug registers are to cause a trigger event to be transmitted to the trigger unit in response to a result of an address comparison with the address associated with debug operations. Claims 7 and 15 depend on the allowable subject matter of Claims 6 and 14, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Strong et al. (U.S. PGPub No. 20180004628) discloses a system performing performance monitoring interrupt handling [Fig. 20], where triggering architecture includes providing observability features such as traces to trigger new actions [0045].
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/A.E.W./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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