DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 01, 2023 and October 22, 2023 are in compliance with the provisions of 37 CFR 1.97 and has been considered by the examiner.
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because text in figures 6-8 are illegible due to text on a grayscale drawing. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities: In claim 1 line 5, "within first set of chiplets of the plurality", should read "within a first set of the plurality of chiplets". In claim 1 line 7, "within a second set of chiplets of the plurality", should read "within a second set of the plurality of chiplets". Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5-6, 9-10, 11, 15-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li J., (US. Patent Application Publication US 20200372345 A1) filed on February 14, 2020, (hereafter Li), in view of Pfeil T., (US. Patent Application Publication US 20210065010 A1) filed on August 20, 2020, (hereafter Pfeil).
Claim 1:
Regarding claim 1, Li teaches “A method for training and fine-tuning an artificial intelligence model, the method comprising: implementing, …frozen layers of the deep neural network;”
See Li in paragraph [0047] where it describes “The adaptation process can be considered a fine-tuning process of the model.” Here, Li establishes a method of fine-tuning of a model. Further, see Li in paragraph [0032] describing “The neural network includes at least one additional layer that is introduced to the pre-trained neural network within the plurality of hidden layers of the pre-trained neural network. The neural network can be trained in accordance with the following protocol: (i) keep weights that are applied to each of the nodes in the hidden layers of the pre-trained neural network frozen and unchanged” Here, Li describes the implementation of layers in a neural network being hidden or frozen.
Further, Li teaches, “implementing, …trainable layers of the deep neural network”
See Li in paragraph [0012] where it describes “Training the pre-trained neural network comprises: introducing at least one additional layer to the plurality of hidden layers, wherein said additional layer has one or more nodes having associated weights; keeping weights of the nodes in the plurality of hidden layers of the pre-trained neural network unchanged; inputting data from a target domain to the input layer; and adjusting weights of the one or more nodes in the at least one additional layer based on features obtained at the output layer.” Here Li establishes trainable layers being implemented of a neural network.
However, Li did not explicitly teach “distributing, across a plurality of chiplets of a package, functionality associated with a deep neural network; implementing, within first set of chiplets of the plurality; and implementing, within a second set of chiplets of the plurality.”
In the same field of art, Pfeil teaches, “distributing, across a plurality of chiplets of a package, functionality associated with a deep neural network;”
See Pfeil in paragraph [0031] where it describes “As a result of the distribution of a functionality (all neurons) of the layers of the deep neural network in sub-functionalities (groups of neurons) among a multitude of processing units, energy may be saved during the deactivation of individual processing units.” Here Pfeil explicitly teaches a distribution of functionality associated with a deep neural network. This is done over multiple processing units which can be seen as chiplets.
In the same field of art and in an analogous system, Pfeil teaches, “implementing, within first set of chiplets of the plurality…layers of the deep neural network;”
See Pfeil in paragraph [0029] where it describes “It is furthermore provided that each layer of the deep neural network includes a multitude of neurons, all neurons of each layer being divided into a multitude of groups. Each of the groups is executed on a processing unit assigned to it. The processing unit in each case processes at least one group of a layer or multiple groups of different layers.” Here Pfeil teaches an implementation of layers on processing units based on what group they are a part of which can insinuate a first set of processing units implementing a group of layers. Processing units can be seen as chiplets, as known in the art.
In the same field of art and in an analogous system, Pfeil teaches, “implementing, within a second set of chiplets of the plurality… layers of the deep neural network;”
See Pfeil in paragraph [0029] where it describes “It is furthermore provided that each layer of the deep neural network includes a multitude of neurons, all neurons of each layer being divided into a multitude of groups. Each of the groups is executed on a processing unit assigned to it. The processing unit in each case processes at least one group of a layer or multiple groups of different layers.” Here once again Pfeil teaches an implementation of layers on processing units based on what group they are a part of which can insinuate another or second set of processing units implementing a different group of layers. Processing units can be seen as chiplets, as known in the art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li with the teachings of Pfeil by using Li’s teachings of implementing frozen and trainable layers, and incorporate with Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets.
One of ordinary skill in the art would be motivated to do so because by integrating Pfeil’s frameworks into the methods of Li, which are both in relation to deep neural network training, one of ordinary skill in the art would bring “a method for compressing a deep neural network, using a skip connection” (Pfeil, paragraph [0002]).
Claim 5:
Regarding claim 5, Li in view of Pfeil teaches the limitations in claim 1.
Further, Li teaches “The method of claim 1, wherein the frozen layers are layers with frozen weights.”
See Li in paragraph [0032] where it describes, “The neural network can be trained in accordance with the following protocol: (i) keep weights that are applied to each of the nodes in the hidden layers of the pre-trained neural network frozen and unchanged” Here, Li establishes the hidden layers which can be seen as frozen comprising weights that are frozen.
Claim 6:
Regarding claim 6, Li in view of Pfeil teaches the limitations in claim 1.
Further, Li teaches “The method of claim 1, wherein the trainable layers are layers with adjustable weights.”
See Li in paragraph [0032] where it describes, “(ii) select most confident samples (i.e. features with least training errors) from a target domain for training each of the at least one additional layer; and (iii) during each training iteration, adjust weights that are applied to each of the nodes in each of the at least one additional layer based on the selected most confident samples.” Here, Li establishes at least one additional layer which can be trained which teaches trainable layers being able to have adjustable weights.
Claim 9:
Regarding claim 9, Li in view of Pfeil teaches the limitations in claim 1.
Further, Li teaches “The method of claim 1, wherein the chiplets of the first set are temporarily reprogrammed to include trainable layers during training of the deep neural network.”
See Li in paragraph [0032] where it describes, “(ii) select most confident samples (i.e. features with least training errors) from a target domain for training each of the at least one additional layer; and (iii) during each training iteration, adjust weights that are applied to each of the nodes in each of the at least one additional layer based on the selected most confident samples.” Here, Li establishes at least one additional layer which can be trained which teaches trainable layers being able to have adjustable weights. Further, see Li in paragraph [0033] where it describes, “At least one additional layer can be introduced to the pre-trained neural network in parallel with the last hidden layer of the pre-trained neural network. A concatenation of the output from the at least one additional layer and the output from the last hidden layer of the pre-trained neural network is passed on to the output layer.” Here, Li establishes the already pre-trained neural network with hidden layers to include trainable layers in parallel which implies during training of the deep neural network. In claim 1 we already established that the set of chiplets used for hidden layers differ from the adjustable layers. The set is temporarily reprogrammed as once it includes the trainable layers with the hidden layers, the output is passed to the output layer insinuating a temporary concatenation.
Claim 10:
Regarding claim 10, Li in view of Pfeil teaches the limitations in claim 9.
Further, Li teaches “The method of claim 9, wherein the chiplets that are temporarily reprogrammed are configured to perform fine-tuning for different inference tasks, the different inference tasks comprising at least one of sentiment analysis, question and answer, instruction following, image classification, and image segmentation.”
See Li in paragraph [0031] where it describes, “According to one embodiment, there is provided a neural network that is used to extract face features from face images when deployed overseas. The neural network includes a pre-trained neural network that is trained with face image data from a source domain. The pre-trained neural network includes an input layer, a plurality of hidden layers and an output layer.” Here, Li establishes the neural network which in previous limitations establishes having a plurality of chiplets and a set that is temporarily configured. This neural network can perform an inference task as described for extracting features from face images which can be seen as image segmentation. Further see Li in paragraph [0010] where it describes, “In order to improve performance of a face recognition system when a “home-brewed” pre-trained model is deployed overseas, embodiments of the invention utilize a domain adaptation technique. The domain adaptation technique involves modifying or tuning a pre-trained model that is trained on a source domain”. Here, Li further establishes the embodiments of the invention which consists of the neural network, performing fine-tuning for a facial recognition system which is an inference tasks for image segmentation.
Claim 11:
Regarding claim 11, Li teaches “An apparatus for training and fine-tuning an artificial intelligence model, the apparatus comprising: … hosting frozen layers of the deep neural network;”
See Li in paragraph [0047] where it describes “The adaptation process can be considered a fine-tuning process of the model.” Here, Li establishes a method of fine-tuning of a model. Further, see Li in paragraph [0071] where it describes “FIG. 5 shows a schematic diagram of a computer system suitable for use in executing at least some steps of the method for training a neural network used to extract face features from face images.” Here, Li establishes a computer system for implementing the method which can be seen as an apparatus. Further, see Li in paragraph [0032] describing “The neural network includes at least one additional layer that is introduced to the pre-trained neural network within the plurality of hidden layers of the pre-trained neural network. The neural network can be trained in accordance with the following protocol: (i) keep weights that are applied to each of the nodes in the hidden layers of the pre-trained neural network frozen and unchanged” Here, Li describes the implementation of layers in a neural network being hidden or frozen.
Further, Li teaches, “… hosting trainable layers of the deep neural network”
See Li in paragraph [0012] where it describes “Training the pre-trained neural network comprises: introducing at least one additional layer to the plurality of hidden layers, wherein said additional layer has one or more nodes having associated weights; keeping weights of the nodes in the plurality of hidden layers of the pre-trained neural network unchanged; inputting data from a target domain to the input layer; and adjusting weights of the one or more nodes in the at least one additional layer based on features obtained at the output layer.” Here Li establishes trainable layers being implemented of a neural network.
However, Li did not explicitly teach “a package comprising a plurality of chiplets, wherein functionality associated with a deep neural network is distributed across the chiplets; a first set of chiplets of the plurality of chiplets hosting…; and a second set of chiplets of the plurality of chiplets hosting…”
In the same field of art, Pfeil teaches, “a package comprising a plurality of chiplets, wherein functionality associated with a deep neural network is distributed across the chiplets;”
See Pfeil in paragraph [0031] where it describes “As a result of the distribution of a functionality (all neurons) of the layers of the deep neural network in sub-functionalities (groups of neurons) among a multitude of processing units, energy may be saved during the deactivation of individual processing units.” Here Pfeil explicitly teaches a distribution of functionality associated with a deep neural network. This is done over multiple processing units which can be seen as chiplets.
In the same field of art, Pfeil teaches, “a first set of chiplets of the plurality of chiplets hosting… layers of the deep neural network;”
See Pfeil in paragraph [0029] where it describes “It is furthermore provided that each layer of the deep neural network includes a multitude of neurons, all neurons of each layer being divided into a multitude of groups. Each of the groups is executed on a processing unit assigned to it. The processing unit in each case processes at least one group of a layer or multiple groups of different layers.” Here Pfeil teaches a hosting of layers on processing units based on what group they are a part of which can insinuate a first set of processing units hosting a group of layers. Processing units can be seen as chiplets, as known in the art.
In the same field of art, Pfeil teaches, “a second set of chiplets of the plurality of chiplets hosting… layers of the deep neural network;”
See Pfeil in paragraph [0029] where it describes “It is furthermore provided that each layer of the deep neural network includes a multitude of neurons, all neurons of each layer being divided into a multitude of groups. Each of the groups is executed on a processing unit assigned to it. The processing unit in each case processes at least one group of a layer or multiple groups of different layers.” Here once again Pfeil teaches a hosting of layers on processing units based on what group they are a part of which can insinuate another or second set of processing units hosting a different group of layers. Processing units can be seen as chiplets, as known in the art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li with the teachings of Pfeil by using Li’s teachings of implementing frozen and trainable layers, and incorporate with Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets.
One of ordinary skill in the art would be motivated to do so because by integrating Pfeil’s frameworks into the methods of Li, which are both in relation to deep neural network training, one of ordinary skill in the art would bring “a method for compressing a deep neural network, using a skip connection” (Pfeil, paragraph [0002]).
Claim 15:
Regarding claim 15, Li in view of Pfeil teaches the limitations in claim 11.
Further, Li teaches “The apparatus of claim 11, wherein the frozen layers are layers with frozen weights.”
See Li in paragraph [0032] where it describes, “The neural network can be trained in accordance with the following protocol: (i) keep weights that are applied to each of the nodes in the hidden layers of the pre-trained neural network frozen and unchanged” Here, Li establishes the hidden layers which can be seen as frozen comprising weights that are frozen.
Claim 16:
Regarding claim 16, Li in view of Pfeil teaches the limitations in claim 11.
Further, Li teaches “The apparatus of claim 11, wherein the trainable layers are layers with adjustable weights.”
See Li in paragraph [0032] where it describes, “(ii) select most confident samples (i.e. features with least training errors) from a target domain for training each of the at least one additional layer; and (iii) during each training iteration, adjust weights that are applied to each of the nodes in each of the at least one additional layer based on the selected most confident samples.” Here, Li establishes at least one additional layer which can be trained which teaches trainable layers being able to have adjustable weights.
Claim 19:
Regarding claim 19, Li in view of Pfeil teaches the limitations in claim 11.
Further, Li teaches “The apparatus of claim 11, wherein the chiplets of the first set are temporarily reprogrammed to include trainable layers during training of the deep neural network.”
See Li in paragraph [0032] where it describes, “(ii) select most confident samples (i.e. features with least training errors) from a target domain for training each of the at least one additional layer; and (iii) during each training iteration, adjust weights that are applied to each of the nodes in each of the at least one additional layer based on the selected most confident samples.” Here, Li establishes at least one additional layer which can be trained which teaches trainable layers being able to have adjustable weights. Further, see Li in paragraph [0033] where it describes, “At least one additional layer can be introduced to the pre-trained neural network in parallel with the last hidden layer of the pre-trained neural network. A concatenation of the output from the at least one additional layer and the output from the last hidden layer of the pre-trained neural network is passed on to the output layer.” Here, Li establishes the already pre-trained neural network with hidden layers to include trainable layers in parallel which implies during training of the deep neural network. In claim 1 we already established that the set of chiplets used for hidden layers differ from the adjustable layers. The set is temporarily reprogrammed as once it includes the trainable layers with the hidden layers, the output is passed to the output layer insinuating a temporary concatenation.
Claim 20:
Regarding claim 20, Li in view of Pfeil teaches the limitations in claim 11.
Further, Li teaches “The apparatus of claim 11, wherein the chiplets of the first set include frozen layers during inference operations of the deep neural network.”
See Li in paragraph [0031] where it describes, “According to one embodiment, there is provided a neural network that is used to extract face features from face images when deployed overseas. The neural network includes a pre-trained neural network that is trained with face image data from a source domain. The pre-trained neural network includes an input layer, a plurality of hidden layers and an output layer.” Here, Li establishes the neural network which in previous limitations establishes having a plurality of chiplets and a set that is temporarily configured. This neural network can perform an inference operation as described for extracting features from face images using hidden layers which can be seen as frozen. Further see Li in paragraph [0010] where it describes, “In order to improve performance of a face recognition system when a “home-brewed” pre-trained model is deployed overseas, embodiments of the invention utilize a domain adaptation technique. The domain adaptation technique involves modifying or tuning a pre-trained model that is trained on a source domain”. Here, Li further establishes the embodiments of the invention which consists of the neural network, performing fine-tuning for a facial recognition system which is an inference operation for image segmentation.
Claim(s) 2-4 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Li J., in view of Pfeil T., and further in view of Ramesh S. (US. Patent Application Publication US 20220215235 A1) filed on January 7, 2021, (hereafter Ramesh).
Claim 2:
Regarding claim 2, Li in view of Pfeil teaches the limitations in claim 1.
Neither Li or Pfeil appears to teach “The method of claim 1, further comprising imparting, to the second set of chiplets, at least one of additional memory capacity and additional memory bandwidth compared to the first set of chiplets.”
However, Ramesh teaches “The method of claim 1, further comprising imparting, to the second set of chiplets, at least one of additional memory capacity and additional memory bandwidth compared to the first set of chiplets.”
See Ramesh in paragraph [0019] where it describes, “One example of this is a neural network that is initially (e.g., partially) trained using a memory device that exhibits high capacity but low bandwidth (e.g., a NAND memory device) and then subsequently trained using a high bandwidth memory (e.g., a 3D stacked SDRAM memory device). By leveraging the capacity of a memory device that exhibits high capacity but low bandwidth, training operations involving large sets of training data can be performed to initially train the neural network. However, once initial training operations have been performed on the neural network, it may be beneficial to write the neural network to a high bandwidth memory device where further training operations can be performed more quickly than in the high capacity memory device.” Here, Ramesh establishes additional memory bandwidth in another or second memory device in comparison to a first memory device. Further, see Ramesh in paragraph [0002] where it describes, “Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems.” Here, Ramesh establishes that a memory can be integrated circuits which as known in the art can be considered chiplets. The comparison of the two memory devices can be seen as comparison to two different sets of chiplets.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Ramesh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Ramesh’s teaching of imparting an additional memory bandwidth to another set of chiplets in comparison to a first.
One of ordinary skill in the art would be motivated to do so because by integrating Ramesh’s frameworks into the methods of Li and Pfeil, which are all in relation to neural network training, one of ordinary skill in the art would bring “data management and training of one or more neural networks within multiple memory devices.” (Ramesh, paragraph [0016]).
Claim 3:
Regarding claim 3, Li in view of Pfeil and further in view of Ramesh teaches the limitations in claim 2.
Neither Li or Pfeil appears to teach “The method of claim 2, wherein the additional memory capacity comprises 3D stacked memory capacity.”
However, Ramesh teaches “The method of claim 2, wherein the additional memory capacity comprises 3D stacked memory capacity.”
See Ramesh in paragraph [0019] where it describes, “One example of this is a neural network that is initially (e.g., partially) trained using a memory device that exhibits high capacity but low bandwidth (e.g., a NAND memory device) and then subsequently trained using a high bandwidth memory (e.g., a 3D stacked SDRAM memory device).” Here, Ramesh establishes the additional memory bandwidth potentially being a 3d stacked memory device which is just the additional memory bandwidth comprising a 3d stacked memory capacity.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Ramesh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Ramesh’s teaching of imparting an additional memory bandwidth to another set of chiplets in comparison to a first comprising a 3d stacked memory capacity.
One of ordinary skill in the art would be motivated to do so because by integrating Ramesh’s frameworks into the methods of Li and Pfeil, which are all in relation to neural network training, one of ordinary skill in the art would bring “data management and training of one or more neural networks within multiple memory devices.” (Ramesh, paragraph [0016]).
Claim 4:
Regarding claim 4, Li in view of Pfeil teaches the limitations in claim 1.
Neither Li or Pfeil appears to teach “The method of claim 1, further comprising imparting, to the second set of chiplets, additional processing capacity compared to the first set of chiplets.”
However, Ramesh teaches “The method of claim 1, further comprising imparting, to the second set of chiplets, additional processing capacity compared to the first set of chiplets.”
See Ramesh in paragraph [0082] where it describes, “At block 546, the method 540 can include performing, using the data corresponding to the neural network written to the second memory device, at least a second portion of the training operation for the neural network by determining one or more second weights for the hidden layer of the neural network. As described above, the first memory device or the second memory device has a higher data processing bandwidth than the other of the first memory device or the second memory device.” Here, Ramesh establishes a higher data processing bandwidth, which is additional processing capacity, in another or second memory device in comparison to a first memory device. Further, see Ramesh in paragraph [0002] where it describes, “Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems.” Here, Ramesh establishes that a memory can be integrated circuits which as known in the art can be considered chiplets. The comparison of the two memory devices can be seen as comparison to two different sets of chiplets.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Ramesh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Ramesh’s teaching of imparting an additional memory bandwidth to another set of chiplets in comparison to a first comprising additional processing capacity.
One of ordinary skill in the art would be motivated to do so because by integrating Ramesh’s frameworks into the methods of Li and Pfeil, which are all in relation to neural network training, one of ordinary skill in the art would bring “data management and training of one or more neural networks within multiple memory devices.” (Ramesh, paragraph [0016]).
Claim 12:
Regarding claim 12, Li in view of Pfeil teaches the limitations in claim 11.
Neither Li or Pfeil appears to teach “The apparatus of claim 11, wherein the second set of chiplets include at least one of additional memory capacity and additional memory bandwidth compared to the first set of chiplets.”
However, Ramesh teaches “The apparatus of claim 11, wherein the second set of chiplets include at least one of additional memory capacity and additional memory bandwidth compared to the first set of chiplets.”
See Ramesh in paragraph [0019] where it describes, “One example of this is a neural network that is initially (e.g., partially) trained using a memory device that exhibits high capacity but low bandwidth (e.g., a NAND memory device) and then subsequently trained using a high bandwidth memory (e.g., a 3D stacked SDRAM memory device). By leveraging the capacity of a memory device that exhibits high capacity but low bandwidth, training operations involving large sets of training data can be performed to initially train the neural network. However, once initial training operations have been performed on the neural network, it may be beneficial to write the neural network to a high bandwidth memory device where further training operations can be performed more quickly than in the high capacity memory device.” Here, Ramesh establishes additional memory bandwidth in another or second memory device in comparison to a first memory device. Further, see Ramesh in paragraph [0002] where it describes, “Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems.” Here, Ramesh establishes that a memory can be integrated circuits which as known in the art can be considered chiplets. The comparison of the two memory devices can be seen as comparison to two different sets of chiplets.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Ramesh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Ramesh’s teaching of imparting an additional memory bandwidth to another set of chiplets in comparison to a first.
One of ordinary skill in the art would be motivated to do so because by integrating Ramesh’s frameworks into the methods of Li and Pfeil, which are all in relation to neural network training, one of ordinary skill in the art would bring “data management and training of one or more neural networks within multiple memory devices.” (Ramesh, paragraph [0016]).
Claim 13:
Regarding claim 13, Li in view of Pfeil and further in view of Ramesh teaches the limitations in claim 12.
Neither Li or Pfeil appears to teach “The apparatus of claim 12, wherein the additional memory capacity comprises 3D stacked memory capacity.”
However, Ramesh teaches “The apparatus of claim 12, wherein the additional memory capacity comprises 3D stacked memory capacity.”
See Ramesh in paragraph [0019] where it describes, “One example of this is a neural network that is initially (e.g., partially) trained using a memory device that exhibits high capacity but low bandwidth (e.g., a NAND memory device) and then subsequently trained using a high bandwidth memory (e.g., a 3D stacked SDRAM memory device).” Here, Ramesh establishes the additional memory bandwidth potentially being a 3d stacked memory device which is just the additional memory bandwidth comprising a 3d stacked memory capacity.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Ramesh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Ramesh’s teaching of imparting an additional memory bandwidth to another set of chiplets in comparison to a first comprising a 3d stacked memory capacity.
One of ordinary skill in the art would be motivated to do so because by integrating Ramesh’s frameworks into the methods of Li and Pfeil, which are all in relation to neural network training, one of ordinary skill in the art would bring “data management and training of one or more neural networks within multiple memory devices.” (Ramesh, paragraph [0016]).
Claim 14:
Regarding claim 14, Li in view of Pfeil teaches the limitations in claim 11.
Neither Li or Pfeil appears to teach “The apparatus of claim 11, wherein the second set of chiplets include additional processing capacity compared to the first set of chiplets.”
However, Ramesh teaches “The apparatus of claim 11, wherein the second set of chiplets include additional processing capacity compared to the first set of chiplets.”
See Ramesh in paragraph [0082] where it describes, “At block 546, the method 540 can include performing, using the data corresponding to the neural network written to the second memory device, at least a second portion of the training operation for the neural network by determining one or more second weights for the hidden layer of the neural network. As described above, the first memory device or the second memory device has a higher data processing bandwidth than the other of the first memory device or the second memory device.” Here, Ramesh establishes a higher data processing bandwidth, which is additional processing capacity, in another or second memory device in comparison to a first memory device. Further, see Ramesh in paragraph [0002] where it describes, “Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems.” Here, Ramesh establishes that a memory can be integrated circuits which as known in the art can be considered chiplets. The comparison of the two memory devices can be seen as comparison to two different sets of chiplets.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Ramesh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Ramesh’s teaching of imparting an additional memory bandwidth to another set of chiplets in comparison to a first comprising additional processing capacity.
One of ordinary skill in the art would be motivated to do so because by integrating Ramesh’s frameworks into the methods of Li and Pfeil, which are all in relation to neural network training, one of ordinary skill in the art would bring “data management and training of one or more neural networks within multiple memory devices.” (Ramesh, paragraph [0016]).
Claim(s) 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Li J., in view of Pfeil T., and further in view of Sheikh S. (US. Patent Application Publication US 20240403258 A1) filed on June 5, 2023, (hereafter Sheikh).
Claim 7:
Regarding claim 7, Li in view of Pfeil teaches the limitations in claim 1.
Neither Li or Pfeil appears to teach “The method of claim 1, wherein the second set of chiplets consists of a single chiplet.”
However, Sheikh teaches “The method of claim 1, wherein the second set of chiplets consists of a single chiplet.”
See Sheikh in paragraph [0004] where it describes, “In some embodiments, a multi-chiplet artificial intelligence processor may include a plurality of chiplets each configured to perform a portion of an inference operation by calculating partial sums that are combined to generate an activation output. The processor may also include a plurality of quantization blocks that are implemented on the plurality of chiplets and configured to individually quantize outputs of each of the plurality of chiplets. The plurality of chiplets may include a first chiplet and a second chiplet. An output of the first chiplet may be quantized to a different number of bits than an output of the second chiplet.” Here, Sheikh establishes a plurality of chiplets, in it a first and second chiplet perform two different operations, the second chiplet can be seen as the second set of chiplets of the plurality and since it is a singular chiplet can be seen as a second set of chiplets consisting of a single chiplet.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Sheikh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Sheikh’s teaching of a second set of chiplets consisting of a singular chiplet.
One of ordinary skill in the art would be motivated to do so because by integrating Sheikh’s frameworks into the methods of Li and Pfeil, one of ordinary skill in the art would bring “A chiplet-based architecture [that] may quantize, or reduce, the number of bits at various stages of the data path in an artificial-intelligence (AI) processor. Instead of only quantizing a single dimension, this architecture may leverage the synergy between multiple dimensions to greatly decrease the memory usage and data path bandwidth” (Sheikh, paragraph [0018]).
Claim 8:
Regarding claim 8, Li in view of Pfeil teaches the limitations in claim 1.
Neither Li or Pfeil appears to teach “The method of claim 1, further comprising storing, in a memory device, activations generated by the first set of chiplets for later training of the second set of chiplets.”
However, Sheikh teaches “The method of claim 1, further comprising storing, in a memory device, activations generated by the first set of chiplets for later training of the second set of chiplets.”
See Sheikh in paragraph [0005] where it describes, “a method of performing an activation operation in an AI accelerator pipeline may include performing the activation operation on an input tensor to generate an output tensor, and quantizing the output tensor before the output tensor is stored in a memory.”. Here, Sheikh storing an activation operation in memory which can be seen as a memory device. Further, see Sheikh in paragraph [0055] where it describes, “for a multi-chiplet architecture, the workload may be distributed between a plurality of individual chiplets. The partial sums may be quantized to mixed-precision values using a dynamic quantization function 402. FIG. 8 illustrates a scalable chiplet architecture where partial sums are quantized, according to some embodiments. In a general sense, the multi-chiplet artificial intelligence processor may be arranged into a plurality of chiplets that are each configured to perform a portion of an inference operation by calculating partial sums are combined to generate an activation output.” Here, Sheikh establishes a plurality of chiplets, used to generate actiavtions. Further, see Sheikh in paragraph [0058] where it describes, “More generally, the plurality of chiplets may include a first chiplet in the second chiplet, and the output of the first chiplet media quantized to a different number of bits than the output of the second chiplet.” Here, Sheikh establishes later training of a second chiplet in comparison to another chiplet, the use of an output of one chiplet to later quantize to a different number of bits is training and the output is generated by activations as established before.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Sheikh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Sheikh’s teaching of a second set of chiplets consisting of a singular chiplet.
One of ordinary skill in the art would be motivated to do so because by integrating Sheikh’s frameworks into the methods of Li and Pfeil, one of ordinary skill in the art would bring “A chiplet-based architecture [that] may quantize, or reduce, the number of bits at various stages of the data path in an artificial-intelligence (AI) processor. Instead of only quantizing a single dimension, this architecture may leverage the synergy between multiple dimensions to greatly decrease the memory usage and data path bandwidth” (Sheikh, paragraph [0018]).
Claim 17:
Regarding claim 17, Li in view of Pfeil teaches the limitations in claim 11.
Neither Li or Pfeil appears to teach “The apparatus of claim 11, wherein the second set of chiplets consists of a single chiplet.”
However, Sheikh teaches “The apparatus of claim 11, wherein the second set of chiplets consists of a single chiplet.”
See Sheikh in paragraph [0004] where it describes, “In some embodiments, a multi-chiplet artificial intelligence processor may include a plurality of chiplets each configured to perform a portion of an inference operation by calculating partial sums that are combined to generate an activation output. The processor may also include a plurality of quantization blocks that are implemented on the plurality of chiplets and configured to individually quantize outputs of each of the plurality of chiplets. The plurality of chiplets may include a first chiplet and a second chiplet. An output of the first chiplet may be quantized to a different number of bits than an output of the second chiplet.” Here, Sheikh establishes a plurality of chiplets, in it a first and second chiplet perform two different operations, the second chiplet can be seen as the second set of chiplets of the plurality and since it is a singular chiplet can be seen as a second set of chiplets consisting of a single chiplet.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Sheikh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Sheikh’s teaching of a second set of chiplets consisting of a singular chiplet.
One of ordinary skill in the art would be motivated to do so because by integrating Sheikh’s frameworks into the methods of Li and Pfeil, one of ordinary skill in the art would bring “A chiplet-based architecture [that] may quantize, or reduce, the number of bits at various stages of the data path in an artificial-intelligence (AI) processor. Instead of only quantizing a single dimension, this architecture may leverage the synergy between multiple dimensions to greatly decrease the memory usage and data path bandwidth” (Sheikh, paragraph [0018]).
Claim 18:
Regarding claim 18, Li in view of Pfeil teaches the limitations in claim 11.
Neither Li or Pfeil appears to teach “The apparatus of claim 11, further comprising higher speed interfaces between chiplets of the second set than between chiplets of the first set.”
However, Sheikh teaches “The apparatus of claim 11, further comprising higher speed interfaces between chiplets of the second set than between chiplets of the first set.”
See Sheikh in paragraph [0005] where it describes, “a method of performing an activation operation in an AI accelerator pipeline may include performing the activation operation on an input tensor to generate an output tensor, and quantizing the output tensor before the output tensor is stored in a memory.”. Here, Sheikh storing an activation operation in memory which can be seen as a memory device. Further, see Sheikh in paragraph [0055] where it describes, “for a multi-chiplet architecture, the workload may be distributed between a plurality of individual chiplets. The partial sums may be quantized to mixed-precision values using a dynamic quantization function 402. FIG. 8 illustrates a scalable chiplet architecture where partial sums are quantized, according to some embodiments. In a general sense, the multi-chiplet artificial intelligence processor may be arranged into a plurality of chiplets that are each configured to perform a portion of an inference operation by calculating partial sums are combined to generate an activation output.” Here, Sheikh establishes a plurality of chiplets, used to generate actiavtions. Further, see Sheikh in paragraph [0058] where it describes, “More generally, the plurality of chiplets may include a first chiplet in the second chiplet, and the output of the first chiplet media quantized to a different number of bits than the output of the second chiplet.” Here, Sheikh establishes later training of a second chiplet in comparison to another chiplet, the use of an output of one chiplet to later quantize to a different number of bits is training and the output is generated by activations as established before.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the base reference of Li and Pfiel, with the teachings of Sheikh by using Li’s teachings of implementing frozen and trainable layers, and Pfeil’s teachings of distributing functionality associated with a neural network across a plurality of chiplets, and incorporate with Sheikh’s teaching of a second set of chiplets consisting of a singular chiplet.
One of ordinary skill in the art would be motivated to do so because by integrating Sheikh’s frameworks into the methods of Li and Pfeil, one of ordinary skill in the art would bring “A chiplet-based architecture [that] may quantize, or reduce, the number of bits at various stages of the data path in an artificial-intelligence (AI) processor. Instead of only quantizing a single dimension, this architecture may leverage the synergy between multiple dimensions to greatly decrease the memory usage and data path bandwidth” (Sheikh, paragraph [0018]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASSAN R SESAY whose telephone number is (571)272-8493. The examiner can normally be reached Monday-Friday 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeanette Parker can be reached at (571) 270-3647. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HASSAN RAMADAN SESAY/Examiner, Art Unit 2146
/USMAAN SAEED/Supervisory Patent Examiner, Art Unit 2146
Prosecution Insights