Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 13 is objected to because of the following informalities: the claim recites “wherein the wherein.” Appropriate correction is required.
Claim 15 is objected to because of the following informalities: the claim recites “To do perform.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-10, 13-17 and 20 are rejected under 35 U.S.C. 102a as being anticipated by Valentine et al. WO 2012/134532 (hereinafter Valentine).
As per claim 1, Valentine teaches an apparatus comprising:
decoder circuitry to decode an instance of a single instruction (decode unit 2432, Fig,. 24), the instance of the single instruction to at least include fields for a prefix, an opcode, and addressing information (EVEX prefix, a real opcode field, and a MOD R/M field. The MOD R/m field includes MOD bits 7:6 and register/address operand fields, see paragraph [00163] and [00177]), wherein the prefix and addressing information are to be used by the decoder circuitry to determine support for a particular vector length (EVEX.U at bye 2, bit 2; a context-specific beta field at byte 3, bits 6:4; and that the addressing information includes MOD R/M.MOD bits 7:6. When U=1 and MOD=11, bit 4 of the beta field is interpreted as an RL bit. When RL=0, the remaining two beta bits are interpreted as a vector-length field. Thus, the prefix and MOD addressing bits determine whether the bits are interpreted as vector-length bits and which vector length applies, see paragraph [00193]) for one or more operands of the instance of the single instruction (The vector-length field selects the length of the vector operands. The disclosed values are 00=128 bits, 01=256 bits, and 10=512 bits. The examples identify corresponding XMM, YMM, ZMM source and destination operands, see paragraph [00230], [00236] and [00353]) and the opcode is to indicate one or more operations to perform on the one or more operands (the real opcode field contains the opcode specifying the base operation. As a specific example, the VADDPS opcode specifies adding packed single-precision floating-point values from source operands and storing the result in a destination operand, see paragraph [00344]); and
execution circuitry to execute the decoded instance of the single instruction according to the opcode (The execution engine includes execution units 2460 Fig. 24, including mixed scalar/vector units. The disclosed pipeline uses the instruction fields during decoding and subsequently executes the decoded operation in the execute stage) to do perform one or more operations on one or more operands of the determined vector length (The vector execution unit performs the operation specified by the opcode on the selected 128-,256-, or 512-bit vector operands. The VADDPS examples expressly show the same operation performed using XMM, YMM, or ZMM operands according to the vector-length field, see paragraph [00344]).
As per claim 2, Valentine teaches the apparatus of claim 1, wherein when bit position 20 of the prefix is set to 0, bit position 10 of the prefix is set to 1, and bit positions 7:6 of the addressing information are set to 11, the instance of the single instruction is to have its vector length determined by bits 21-22 of the prefix (EVEX.U/P10=1; MOD=11, RL/P20; and the remaining P22:21 bits are interpreted as the vector-length field. The two bits 128, 256, or 512 bits. See Fig. 18, vectors).
As per claim 3, Valentine teaches the apparatus of claim 1, wherein when bit position 20 of the prefix is set to 1, bit position 10 of the prefix is set to 1, and bit positions 7:6 of the addressing information are set to 11, the instance of the single instruction has a 512-bit vector length and bits 21-22 of the prefix specify a rounding for the instance of the single instruction when U/P10=1, MOD=11, and RL/P20=1, P22:21 specify the rounding operation. It also teaches that instruction templates lacking a separate vector-length selection operate at the maximum supported vector length, which in the disclosed implementation is 512 bits, see paragraph [00142] and Fig. 18s).
As per claim 6, Valentine teaches the apparatus of claim 1, wherein two bits of the prefix specify an embedded rounding mode (see paragraphs [00142], rounding mode and [00192] two-bit round operation field).
As per claim 7, Valentine teaches the apparatus of claim 6, wherein the specified embedded rounding mode is one of round to zero, round to nearest even, round down, or round up (see paragraph [00126]).
As per claims 8 and 15, they are rejected for the same reasons set forth above in claim 1. Furthermore, Valentine discloses processor system containing instruction cache and system memory coupled to the processor, see Fig. 24.
As per claims 9 and 16, they are rejected for same reasons set forth above in claim 2.
As per claims 10 and 17, they are rejected for same reasons set forth above in claim 3.
As per claims 13 and 20, they are rejected for same reasons set forth above in claim 6.
As per claim 14, it’s rejected for the same reasons set forth above in claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 11-12 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine in view of Wolrich et al. US PG-Pub: 2014/0093069 (hereinafter Wolrich).
As per claims 4 and 5, the claims require the instruction to have a 256-bit or 128-bit vector length when prefix bit 10 is zero, MOD R/M bits 7:6 are 11, and prefix bits 21-22 specify rounding.
Valentine discloses the apparatus of claim 1 as previously mapped. Regarding the additional limitations of claims 4 and 5, Valentine discloses:
prefix bit position 10 set to zero: EVEX.U is located at EVEX byte 2, bit 2, corresponding to claim prefix bit 10, and EVEX.U=0 indicates a class-A instruction, see Valentine paragraph [00167] and Fig. 3A.
addressing-information bits 7:6 set to 11: the MOD R/M.MOD field occupies bits 7:6, and MOD=11 indicates a no-memory-access/register instruction, see Valentine paragraph [00176] and [00192] and Figs. 3A and 3D; and
prefix bits 21-22 specifying rounding: when U=0, MOD=11, and the round-type instruction template is selected, EVEX byte 3, bits 6:4 form a round-control field containing a one-bit SAE field and a two-bit round-operation field. The two-bit round-operation field at EVEX byte 3, bits 6:5 corresponds to claimed prefix bits 22:21, see Valentine paragraph [00192] and Fig. 3D.
Valentine does not expressly teach using EVEX byte 3, bit 4 – claimed prefix bit 20 – to select between 128-bit to 256-bit vector lengths in the U=0 round-control instruction template. Valentine instead uses that bit as the SAE field.
Wolrich, however, teaches a known one-bit vector-length encoding. Specifically, Wolrich teaches a VEX.L size field in which:
VEX.L=0 specifies a 128-bit vector; and
VEX.L=1 specifies a 256-bit vector.
See Wolrich, paragraph [0102] and Fig. 9a.
Accordingly, the combined teachings result in an instruction having U/bit 10=0, MOD=11, bit 20=1 or 0 selecting a 128-bit or 256-bit vector length, and bits 21-22 specifying rounding.
It would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to apply Wolrich’s known one-bit 128-/256-bit vector-length encoding to Valentine’s U=0, MOD=11 round-control instruction format. Valentine recognizes that shorter vector lengths are useful and further states that features associated with one instruction class may be implemented in another instruction class, see Valentine paragraph [00152]. A skilled artisan therefore would have been motivated to repurpose Valentine’s one-bit SAE field, when SAE functionality was not required as the vector-length selector taught by Wolrich, while retaining Valentine’s adjacent two-bit round-operation field. Such a modification would support embedded rounding for both 128-bit and 256-bit operands without increasing the instruction length or adding another prefix field. The modification amounts to applying a known one-bit vector-length selection technique to a similar vector instruction format and would have been produced the predictable results of: bit 20=1 [Wingdings font/0xE0] 256-bit vector, as recited in claim 4; and bit 20=0 [Wingdings font/0xE0] 128-bit vector, as recited in claim 5.
As per claims 11 and 12, they are rejected for the same reasons set forth above in claims 4 and 5.
As per claims 18 and 19, they are rejected for the same reasons set forth above in claims 4 and 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PG-Pub: 2018/0081689 teaches a method of improved extract instructions.
US Patent: 9,811,338 teaches flag non-modification extension for ISA instructions using prefixes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm.
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/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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