DETAILED ACTION
This Office Action is in response to an application filed on July 1, 2023, in which claims 1 through 20 are pending, and ready for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 27, 2024 was filed before the mailing date of a first Office Action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities:
Claims 1 and 11 each recite, “…by the first path and second path”.
It appears that the claim(s) should recite, “…by the first path and the second path”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 9, 18, and 19 each recite, “the theta step, the rho step, and the pi step”.
The foregoing recited elements render claims 9, 18, and 19 indefinite because claims 1 and 11 recite each “a theta step”, “a rho step”, and “a pi step” twice, and thus it is unclear as to which of these previously-recited elements the later recitations in claims 9, 18, and 19 refer.
Claim 11 recites, “other SHA3 circuitries”.
It is not explicitly clear where else in claim 11 a recitation of “SHA3 circuitries” appears, thus making it unclear as to why the foregoing recitation references “other” SHA3 circuitries.
Claims 12-19 are each dependent from claim 11, and are therefore rejected under the same rationale based upon that dependency.
Claim 20 recites, “the non-linear X computation”.
There is insufficient antecedent basis for this element in the claim(s).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Roussellet, et al., EP 3 335 366 B1, as provided by Applicant in the Information Disclosure Statement submitted on June 27, 2024 (hereinafter referred to as Roussellet).
With regard to claim 1, Roussellet discloses storage to store a 1600-bit input state (Roussellet, [0005]) a Keccak round (Roussellet, [0048]) datapath coupled to the storage (Roussellet, [0025]), the Keccak round datapath at least including: a first path (Roussellet, [0025]) including a theta step (Roussellet, [0028]), a rho step (Roussellet, [0030]), a pi step (Roussellet, [0031]), and an iota step (Roussellet, [0037]) to process a masked version of the 1600-bit input state (Roussellet, [0025]), a second path (Roussellet, [0025]) including a theta step (Roussellet, [0052]), a rho step (Roussellet, [0054]), and a pi step (Roussellet, [0055]) to process a mask 1600-bit input state (Roussellet, [0025]), and a masked chi step shared by the first path and second path (Roussellet, [0032]; [0056]).
With regard to claim 2, Roussellet further discloses wherein the Keccak round datapath further at least includes storage for a mask (Roussellet, [0012]).
With regard to claim 3, Roussellet further discloses wherein the mask is a random 1600-bit value (Roussellet, [0012]).
With regard to claim 4, Roussellet further discloses wherein the Keccak round datapath further at least includes XOR circuitry to XOR the 1600-bit input state with a mask to generate the masked version of the 1600-bit input state (Roussellet, [0043]).
With regard to claim 5, Roussellet further discloses wherein the Keccak round datapath further at least includes XOR circuitry to XOR output of the first and second paths as an output state (Roussellet, [0043]).
With regard to claim 6, Roussellet further discloses decoder circuitry to decode a Keccak instruction, the Keccak instruction to include at least one field to identify a location of the 1600-bit input state, least one field to identify a location of a 1600-bit output state, and a field for an opcode, the opcode to indicate the Keccak round datapath is to perform a Keccak round calculation (Roussellet, [0002]).
With regard to claim 7, Roussellet further discloses decoder circuitry to decode a Keccak instruction, the Keccak instruction to include at least one field to identify a location of the 1600-bit input state, least one field to identify a location of a 1600-bit output state, and a field for an opcode, the opcode to indicate the Keccak round datapath is to perform a Keccak permutation (Roussellet, [0002]).
With regard to claim 8, Roussellet further discloses wherein the Keccak permutation consists of Keccak rounds (Roussellet, [0005]).
With regard to claim 9, Roussellet further discloses wherein the second path including the theta step, the rho step, and the pi step to process the mask 1600-bit input state and the shared masked chi step are to be used only for a proper subset of Keccak permutation rounds (Roussellet, [0028]-[0031]).
With regard to claim 10, Roussellet further discloses wherein the Keccak round datapath is to be used consecutively for a plurality of Keccak rounds (Roussellet, [0048]).
With regard to claim 11, Roussellet discloses memory to store a 1600-bit input state (Roussellet, [0011]-[0012]); execution circuitry (Roussellet, [0025]; Fig. 1) including: a Keccak round (Roussellet, [0048]) datapath coupled to the memory (Roussellet, [0025]), the Keccak round datapath at least including: a first path (Roussellet, [0025]) including a theta step (Roussellet, [0028]), a rho step (Roussellet, [0030]), a pi step (Roussellet, [0031]), and an iota step (Roussellet, [0037]) to process a masked version of the 1600-bit input state (Roussellet, [0025]), a second path (Roussellet, [0025]) including a theta step (Roussellet, [0052]), a rho step (Roussellet, [0054]), and a pi step (Roussellet, [0055]) to process a mask 1600-bit input state (Roussellet, [0025]), and a masked chi step shared by the first path and second path (Roussellet, [0032]; [0056]); and other SHA3 circuitries (Roussellet, [0025]; Fig. 1).
With regard to claim 12, Roussellet further discloses wherein the Keccak round datapath further at least includes storage for a mask (Roussellet, [0012]).
With regard to claim 13, Roussellet further discloses wherein the mask is a random 1600-bit value (Roussellet, [0012]).
With regard to claim 14, Roussellet further discloses wherein the Keccak round datapath further at least includes XOR circuitry to XOR the 1600-bit input state with the mask to generate the masked version of the 1600-bit input state (Roussellet, [0043]).
With regard to claim 15, Roussellet further discloses wherein the Keccak round datapath further at least includes XOR circuitry to XOR output of the first and second paths as an output state (Roussellet, [0043]).
With regard to claim 16, Roussellet further discloses decoder circuitry to decode a Keccak instruction, the Keccak instruction to include at least one field to identify a location of the 1600-bit input state, least one field to identify a location of a 1600-bit output state, and a field for an opcode, the opcode to indicate the Keccak round datapath is to perform a Keccak round calculation (Roussellet, [0002]).
With regard to claim 17, Roussellet further discloses decoder circuitry to decode a Keccak instruction, the Keccak instruction to include at least one field to identify a location of the 1600-bit input state, least one field to identify a location of a 1600-bit output state, and a field for an opcode, the opcode to indicate the Keccak round datapath is to perform a Keccak permutation (Roussellet, [0002]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: See PTO-892.
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/J. BRANT MURPHY/Primary Examiner, Art Unit 2435
September 5, 2026
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