Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This Office Action is responsive to the communication filed 2/23/2026.
Claim Status
2. Newly added claims 14-15 have been entered.
Allowable Subject Matter
3. Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
4. The applicant’s arguments have been taken into consideration, but are moot in view of the new grounds of rejection.
A. In response to the applicant’s argument (disclosed on pg. 1-3 of the remarks segment) that the cited prior art fails to teach or suggest computing a check value from multiple program instructions as the program instructions are loaded into an instruction buffer memory of the data processing device or after the program instructions have been loaded into the instruction buffer memory from the one or more memories:
The examiner maintains that the computing of a checksum value as a function of data that is read from a target memory location, in which a command including an address of the target memory location is read from an instruction memory (which is obvious in light of an entity containing multiple program instructions) (as disclosed in the abstract of Martorana et al) would be considered obvious to one of ordinary skill in light of “computing a check value from multiple program instructions after the program instructions have been loaded into the instruction buffer memory from the one or more memories” because the checksum value (e.g., “check value”) computed within the disclosure of Martorana et al derives from data that is read from a volatile instruction memory (e.g., instruction buffer memory), via data that is retrieved, by the instruction memory, from one of a plurality of separate memory locations (as disclosed in par [0060-0062] of Martorana et al), e.g., (“after the program instructions have been loaded into the instruction buffer memory from the one or more memories”).
B. In response to the applicant’s argument (disclosed on pg. 4-5 of the remarks segment) that the cited prior art fails to teach or suggest wherein the check value is derived from a key concealed in the data processing device:
The examiner maintains that a check value computed from a key authentication key and an encryption key (as disclosed in par [0106] of prior art reference Hughes et al (US 2013/0083926)) because the keys in which the check value are computed from are contained within the same user’s device (e.g., “derived from a key concealed in the data processing device”, as also disclosed in par [0106] of Hughes et al).
C. In response to the applicant’s argument (disclosed on pg. 5 of the remarks segment) that the cited prior art fails to teach or suggest computing the check value when the program instructions are loaded from the one or more memories into the instruction buffer memory by way of read access to a transmission path between the one or more memories and the instruction buffer memory:
The rejection of claim 5 (which discloses the limitation in question) has been withdrawn.
Claim Rejections – 35 USC 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-3 and 6-13 are rejected under 35 USC 103 as being unpatentable over Hufnagel et al (DE 102016223341 A1) in view of Meyer (US 2021/0240563), further in view of Martorana et al (US 2022/0308545).
Regarding claim 1, Hufnagel et al teaches a method for executing a program on a data processing device (par [0002], lines 5-8), the method comprising:
storing multiple program instructions and data to be processed by a processor of the data processing device in one or more memories of the data processing device (fig. 1a-1b & par [0034], lines 1-4, “data stored in the memory units”);
storing the reference value in the data processing device (par [0018], lines 1-5, “stored comparison checksum”); and
the processor executing at least some of the program instructions if the check value matches the received reference value (par [0005], lines 3-7, par [0018-0020], and par [0044], which disclose forwarding data to a processing unit if the pre-stored comparison checksum matches the calculated checksum value).
Hufnagel et al does not explicitly teach the data processing device receiving, from an external data processing device, a reference value for a check of the multiple program instructions.
However, Meyer teaches the data processing device receiving, from an external data processing device, a reference value for a check of the multiple program instructions (par [0011], lines 5-15, which discloses receiving a reference checksum value from an external device).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Meyer within the disclosure of Hufnagel et al in order to provide the predictive result of improving prevention of program data manipulation by utilizing a controller in addition to a processor device to perform checksum reference value comparison (as disclosed in par [0011] of Meyer) because allowing the processor device to perform the checksum comparison is suspectable to being manipulated by a hacker (as disclosed in par [0011] of Meyer).
Hufnagel et al and Meyer do not explicitly teach computing a check value from the multiple program instructions for the check by way of the data processing device when the program instructions are loaded from the one or more memories into an instruction buffer memory of the data processing device or by way of read access to the instruction buffer memory after the program instructions have been loaded into the instruction buffer memory from the one or more memories.
However, Martorana et al teaches computing a check value from the multiple program instructions for the check (Abstract, which discloses computing checksum values for comparison to stored checksum values) by way of the data processing device when the program instructions are loaded from the one or more memories into an instruction buffer memory of the data processing device or by way of read access to the instruction buffer memory after the program instructions have been loaded into the instruction buffer memory from the one or more memories (par [0011], lines 6-15, which discloses the checksum value being computed as a function of data read from a target memory location corresponding to an address read from instruction memory).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Martorana et al within the teachings of Hufnagel et al and Meyer in order to provide the predictive result of further improving preventing unauthorized tampering of data when triggering an alarm in response to a detected mismatch of computed checksum data (as disclosed in the Abstract of Martorana et al) because implementing this feature would decrease unauthorized access to secure data by automatically denying access upon the alert signifying a checksum value mismatch being generated.
Regarding claim 2, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 1.
Hufnagel et al further teaches storing the reference value in a write-protected memory region of the data processing device (par [0018], lines 1-5, which discloses storing the comparison checksum in ROM).
Regarding claim 3, Hufnagel et al does not explicitly teach wherein the check value is a cryptographic check value.
However, Meyer teaches wherein the check value is a cryptographic check value (par [0040], lines 1-5, “hash value is calculated as a reference checksum”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Meyer within the disclosure of Hufnagel et al according to the motivation disclosed regarding claim 1.
Regarding claim 5, Hufnagel et al Meyer do not explicitly teach computing the check value when the program instructions are loaded from the one or more memories into the instruction buffer memory by way of read access to a transmission path between the one or more memories and the instruction buffer memory.
However, Martorana et al teaches computing the check value when the program instructions are loaded from the one or more memories into the instruction buffer memory by way of read access to a transmission path between the one or more memories and the instruction buffer memory (Abstract, which discloses the checksum values being computed as a function of data that is read from the target memory location).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Martorana et al within the teachings of Hufnagel et al and Meyer according to the motivation disclosed regarding claim 1.
Regarding claim 6, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 1.
Hufnagel et al further teaches storing the reference value in a write-protected memory region of the data processing device (par [0018], lines 1-5, which discloses the comparison checksum in ROM) and the processor comparing the check value with the reference value (par [0018], lines 1-2, which discloses comparing the calculated checksum with the stored checksum).
Regarding claim 7, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 1.
Hufnagel et al further teaches comprising a checking unit, which computes the check value, comparing the check value with the reference value (par [0019], “comparing the calculated checksum with the comparison checksum”).
Regarding claim 8, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 1.
Hufnagel et al further teaches outputting a signal and/or performing a security measure if the check value does not match the reference value (par [0045], which discloses indicating an error diagnosis upon determining that the calculated checksum with the comparison checksum do not match).
Regarding claim 9, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 1.
Hufnagel et al further teaches wherein a respective reference value is received for each of multiple program code portions each containing multiple program instructions of a program (par [0021], “comparison checksum is created and stored”), a check value is computed when the program code portion is loaded into the instruction buffer memory (par [0020], lines 5-8, “comparison checksum is advantageously calculated and stored”) or by way of read access to the instruction buffer memory after the program code portion has been loaded into the instruction buffer memory, and wherein, for each of the multiple program code portions, at least part of the program code portion is executed by the processor if the check value computed for the program code portion matches the reference value received for the program code portion (par [0044], forwarding data if there is a match between the current checksum and a comparison checksum).
Regarding claim 10, Hufnagel et al teaches data processing device (fig. 1A) comprising:
a processor (fig. 1A);
one or more memories that are configured to store multiple program instructions and data to be processed by a processor of the data processing device (fig. 1a-1b & par [0034], lines 1-4, “data stored in the memory units”);
an instruction buffer memory for buffer-storing the program instructions to be executed by the processor (par [0007]);
a data buffer memory for buffer-storing the data to be processed (par [0034], lines 1-5, “designed to execute processes…depending on data stored in the memory units”);
store a reference value in the one or more memories (par [0018], lines 1-5, “stored comparison checksum”); and
wherein the processor is configured to execute at least some of the program instructions if the check value matches the received reference value (par [0005], lines 3-7, par [0018-0020], and par [0044], which disclose forwarding data to a processing unit if the pre-stored comparison checksum matches the calculated checksum value).
Hufnagel et al does not explicitly teach a communication interface to an external data processing device, which communication interface is configured to receive a reference value for a check of the multiple program instructions from the external data processing device.
However, Meyer teaches a communication interface to an external data processing device, which communication interface is configured to receive a reference value for a check of the multiple program instructions from the external data processing device (par [0011], lines 5-15, which discloses receiving a reference checksum value from an external device).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Meyer within the disclosure of Hufnagel et al in order to provide the predictive result of improving prevention of program data manipulation by utilizing a controller in addition to a processor device to perform checksum reference value comparison (as disclosed in par [0011] of Meyer) because allowing the processor device to perform the checksum comparison is suspectable to being manipulated by a hacker (as disclosed in par [0011] of Meyer).
Hufnagel et al and Meyer do not explicitly teach checking circuitry configured to compute a check value from the multiple program instructions for the check by way of the data processing device when the program instructions are loaded from the one or more memories into an instruction buffer memory of the data processing device or by way of read access to the instruction buffer memory after the program instructions have been loaded into the instruction buffer memory from the one or more memories.
However, Martorana et al teaches circuitry configured to compute a check value from the multiple program instructions for the check (Abstract, which discloses computing checksum values for comparison to stored checksum values) by way of the data processing device when the program instructions are loaded from the one or more memories into an instruction buffer memory of the data processing device or by way of read access to the instruction buffer memory after the program instructions have been loaded into the instruction buffer memory from the one or more memories (par [0011], lines 6-15, which discloses the checksum value being computed as a function of data read from a target memory location corresponding to an address read from instruction memory).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Martorana et al within the teachings of Hufnagel et al and Meyer in order to provide the predictive result of further improving preventing unauthorized tampering of data when triggering an alarm in response to a detected mismatch of computed checksum data (as disclosed in the Abstract of Martorana et al) because implementing this feature would decrease unauthorized access to secure data by automatically denying access upon the alert signifying a checksum value mismatch being generated.
Regarding claim 11, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 10.
Hufnagel et al further teaches wherein the instruction buffer memory has access for the processor that is faster in comparison with the one or more memories (par [0024], lines 5-10, “cache of the processor unit”).
Regarding claim 12, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 10.
Hufnagel et al further teaches wherein the checking unit is configured to compare the check value with the reference value (par [0019], “comparing the calculated checksum with the comparison checksum”) and to output a signal to another component of the data processing device if the check value does not match the reference value (par [0045], which discloses indicating an error diagnosis upon determining that the calculated checksum with the comparison checksum do not match).
Regarding claim 13, Hufnagel et al, Meyer, and Martorana et al teach the limitations of claim 10.
Hufnagel et al further teaches wherein the instruction buffer memory is a cache memory (par [0018], lines 8-10, “checksum cache”) or a tightly coupled RAM (par [0018], lines 1-5, which discloses that the checksum data may be stored in RAM).
7. Claim 4 is rejected under 35 USC 103 as being unpatentable over Hufnagel et al (DE 102016223341 A1) in view of Meyer (US 2021/0240563), in view of Martorana et al (US 2022/0308545), further in view of Hughes et al (US 2013/0083926).
Regarding claim 4, Hufnagel et al, Meyer, and Martorana et al do not explicitly teach wherein the check value is derived from a key concealed in the data processing device.
However, Hughes et al teaches wherein the check value is derived from a key concealed in the data processing device (par [0106], which discloses the user device computing the check value from the device’s own cryptographic keys).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Hughes et al within the teachings of Hufnagel et al and Meyer in order to provide the predictive result of improving generating check value-based authentication by implementing a trusted authority (as disclosed in the Abstract of Hughes et al) for further ensuring that the generated check values correspond to the previously stored, secure check values.
8. Claims 14-15 are rejected under 35 USC 103 as being unpatentable over Hufnagel et al (DE 102016223341 A1) in view of Meyer (US 2021/0240563), in view of Martorana et al (US 2022/0308545), further in view of Giraud et al (EP 1538509 A1).
Regarding claim 14, Hufnagel et al, Meyer, and Martorana et al do not explicitly teach wherein the checking circuitry is configured to compute the check value from the program instructions as the program instructions are loaded from the one or more memories into the instruction buffer memory.
However, Giraud et al teaches wherein the checking circuitry is configured to compute the check value from the program instructions as the program instructions are loaded from the one or more memories into the instruction buffer memory (fig. 1 & pg. 4, lines 33-39, which discloses calculating a checksum on instruction content simultaneously with instructions being executed and recorded via memory).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Giraud et al within the teachings of Hufnagel et al, Meyer, and Martorana et al, in order to provide the predictive result of improving verification of checksum integrity by implementing sums verification and performing a pre-calculation of checksums on each portion of code to be protected (as disclosed in pg. 5, lines 7-15 of Giraud et al).
Regarding claim 15, Hufnagel et al, Meyer, and Martorana et al do not explicitly teach wherein said computing the check value from the multiple program instructions for the check is performed as the program instructions are loaded from the one or more memories into the instruction buffer memory.
However, Giraud et al teaches wherein said computing the check value from the multiple program instructions for the check is performed as the program instructions are loaded from the one or more memories into the instruction buffer memory (fig. 1 & pg. 4, lines 33-39, which discloses calculating a checksum on instruction content simultaneously with instructions being executed and recorded via memory).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Giraud et al within the teachings of Hufnagel et al, Meyer, and Martorana et al, in order to provide the predictive result of improving verification of checksum integrity by implementing sums verification and performing a pre-calculation of checksums on each portion of code to be protected (as disclosed in pg. 5, lines 7-15 of Giraud et al).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Randy A. Scott whose telephone number is (571) 272-3797. The examiner can normally be reached on Monday-Thursday 7:30 am-5:00 pm, second Fridays 7:30 am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Luu Pham can be reached on (571) 270-5002. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RANDY A SCOTT/Primary Examiner, Art Unit 2439 20260601
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