DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the America Invents Act (AIA ).
Response and Claim Status
The instant Office action is responsive to the interview conducted January 16, 2026 (the Interview) and the response received February 23, 2026 (the Response).
In response to the Interview and the Response, the previous (1) rejection of claims 3, 5, 7-11, and 13–15 under 35 U.S.C. § 102; and (2) rejection of claims 2, 4, 16, and 17 under 35 U.S.C. § 103
are WITHDRAWN.
Claims 1–11 and 13–20 are currently pending.
Claim Rejections – 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 20 are rejected under 35 U.S.C. § 102 as being anticipated by Pham et al., Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining, IEEE Access, Vol. 8, pp. 139634–139646 (Aug. 2020).
Response to Arguments
Applicants assert
Pham explains that “each clock cycle computes one Wⱼ value.” Pham, p. 37. Then Pham derives algebraic simplifications of the standard SHA-256 message schedule, such as rewriting W20=σ1(W18)+W13+σ0(W5)+W4 as W20= σ1(W18)+C when W4 is a constant C, and W 5 through W20 are zero.” Response 9.
In Pham’s compact message expander, the clock cycle that produces W20 is still executed. In Pham, the architecture simply evaluates a simplified expression for W20 in that cycle. Likewise, W4, W5, W13, and the other Wⱼ values are still produced in their respective cycles (the first 16 loops assign Wj=Mj), even if some of those values are known constants or zeros. Thus, Pham optimizes the logic within each message-expansion cycle but does not disclose an architecture in which a subset of message-expansion cycles is omitted from the schedule or “removed” altogether. Even when the cycle is simplified, it is still computed.
Response 9.
Applicants argue
[t]his fails to teach or suggest the currently amended claims because, in Pham, each cycle is still computed, just with simplified arithmetic within cycles. Pham’s compact message expander, therefore, does not anticipate or render obvious the claimed “executing the modified plurality of message expansion computations includes replacing the at least one message expansion computation of the plurality of message expansion computations with the at least one constant and wherein replacing the at least one message expansion computation with the at least one constant includes removing a plurality of cycles of the plurality of message expansion computations.[“ sic]
Id. at 9–10.
The Examiner is unpersuaded of error. In light of Applicants’ amendment to claim 1, the Examiner has reconsidered Pham as a whole.
At the outset, the Examiner agrees with Applicants that Pham disclosing “[e]ach clock cycle computes one Wj value” results in each cycle being computed. Pham 37. The Examiner finds Pham disclosing “[e]ach clock cycle computes one Wj value.” applies to SHA-2561. See id. Pham’s SHA-2561 involves “produc[ing] one hash value every 64 clock cycles.” Id. In particular, “SHA-2561 . . . calculat[es] Wj (j = 0, . . . , 63) and . . . calculat[es] the internal hashes a, b, c, d, e, f , h in 64 clock cycles.” Id.
But the 103 rejection relies on Pham’s disclosure of SHA-2562, not SHA-2561. In particular, the 103 rejection relies on Pham’s disclosure of a compact message expander (CME) algorithm for SHA-2562 “[t]o reduce the hardware and power costs of SHE-2562.” Pham 37. Pham’s disclosure of the CME algorithm for SHA-2562 is disclosed in Pham’s section III(B)(1). See id. at 37–38. Pham’s section III(B)(1) discloses replacing at least one Wj (the claimed “message expansion computation”) with at least one C or 0 (the claimed “constant”). See id.
Pham’s “SHA-2562 . . . can produce an output hash every clock cycle.” Pham 37; see also id. at 35 (reciting “Our architecture generates one 256-bit
hash value per clock cycle.”). Thus, Pham’s SHA-2562 calculates all its Wj’s in one clock cycle as opposed to SHA-2561 that calculates all its Wj’s in 64 clock cycles. Therefore, Pham discloses replacing at least one Wj (the claimed “message expansion computation”) with at least one C or 0 (the claimed “constant”) includes removing a plurality of clock cycles of the Wj’s (to just one clock cycle when compared to the 64 clock cycles required to compute the Wj’s for SHA-2561). Accordingly, Pham discloses “wherein replacing the at least one message expansion computation with the at least one constant includes removing a plurality of cycles of the plurality of message expansion computations,” as recited in claim 1.
The Rejection
Regarding claim 1, Pham discloses a method of secure data hashing using an apparatus (fig. 16, “Host PC” at p. 44) including at least one of a message compressor (MC) or a message expander (ME) (“SHA-256 consists of a message expander (ME) and a message compressor (MC)” at p. 34), the method comprising:
receiving word data (“16 32-bit words Mj (j = 0, . . . , 15)” at p. 38) associated with a message (“512-bit input message” at p. 34; “the 512 bits of data” at p. 38);
identifying a plurality of message expansion computations (“During the first 16 loops, Wj (j = 0, . . . , 15) are assigned to Mj (j = 0, . . . , 15).” and “During the last 48 loops, the CME calculates Wj (j = 16, . . . , 63) by using (7): Wj = σ1(Wj−2) + Wj−7 + σ0(Wj−15) + Wj−16.” at p. 38) that are configured to use the word data to generate a hash (“hash output from SHA-2562” at p. 38) for the message using a secure hash algorithm (SHA) (“SHA-256” at p. 34);
pre-computing at least one message expansion computation (“the zeros or constant values of Wj (j = 4, . . . , 15)” at p. 38) of the plurality of message expansion computations using the word data to generate at least one constant (“W4 and W15 are constants” at p. 38); and
executing, after the at least one constant is pre-computed (the calculation of various Wj in Algorithm 3 at p. 38 is dependent on prior calculated constants), a modified plurality of message expansion computations (“Utilizing the zeros or constant values of Wj (j = 4, . . . , 15), we can optimize the calculation of (7)” at p. 38; Algorithm 3 at p. 38) to generate the hash of the message using the SHA, wherein executing the modified plurality of message expansion computations includes replacing the at least one message expansion computation (“W16 = σ1(W 14) + W 9 + σ0(W 1) + W 0” at equation (8), p. 38) of the plurality of message expansion computations with the at least one constant (“W16 = σ1(W 14) + W 9 + σ0(W 1) + W 0” at equation (8), p. 38 becomes “= 0 + 0 + σ0(W1) + W0” at equation (8), p. 38 wherein the clock cycles that were to compute W 14 + W 9 are replaced with prior calculated 0;
for example, W20 = σ1(W 18) + W 13 + σ0(W 5) + W 4 according to equation (7) and because W4 is a constant C and W5 to W14 are zero, then
W20 = σ1(W 18) + W 13 + σ0(W 5) + W 4
= σ1(W 18) + 0 + 0 + C
= σ1(W 18) + C
, wherein the clock cycles that were to compute W 13, W 9, and W 4 are replaced with, respectively, prior calculated 0, 0, and C) and wherein replacing the at least one message expansion computation with the at least one constant includes removing a plurality of cycles (applying SHA-2562 reduces a plurality of clock cycles to one clock cycle over the 64 clock cycles for SHA-2561 and up to 64 clock cycles for prior hardware circuits; “the hardware circuits developed in [7]–[22] . . . require several (up to 64) clock cycles to compute a single 256-bit hash value.” at p. 35; “SHA-2561 involves “produc[ing] one hash value every 64 clock cycles.” At p. 37; “SHA-2562 . . . can produce an output hash every clock cycle.” at p. 37) of the plurality of message expansion computations.
Regarding claim 20, Pham discloses a system (fig. 16, “Host PC” at p. 44) for secure data hashing, the system comprising:
at least one memory (one skilled in the art would reasonably be expected to infer fig. 16, “Host PC” at p. 44 includes memory; see MPEP § 2144.01); and
at least one processor (one skilled in the art would reasonably be expected to infer fig. 16, “Host PC” at p. 44 includes a processor) coupled to the at least one memory, the at least one processor configured to perform operations according to claim 1. Thus, references/arguments equivalent to those present for claim 1 are equally applicable to claim 20.
Claim Rejections – 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. § 103 as being obvious over Pham.
Regarding claim 2, while Pham teaches pre-computing the at least one message expansion computation (“the zeros or constant values of Wj (j = 4, . . . , 15)” at p. 38) to generate the at least one constant (“W4 and W15 are constants” at p. 38),
Pham does not teach wherein pre-computing the at least one message expansion computation to generate the at least one constant includes removing a term from the at least one message expansion computation, wherein the term is equal to zero.
Pham teaches removing a term from at least one message expansion computation (p. 38, equation (8) teaches
W16 = σ1(W 14) + W 9 + σ0(W 1) + W 0
= 0 + 0 + σ0(W 1) + W 0
= σ0(W 1) + W 0
), wherein the term is equal to zero.
It would have been prima facie obvious to one of ordinary skill in the art before the effective date of the invention for Pham’s pre-computing of the at least one message expansion computation to generate the at least one constant to include removing a term from the at least one message expansion computation, wherein the term is equal to zero as taught by Pham “for reducing the hardware cost and power consumption of high processing rate fully unrolled SHA-256 architecture.” Pham p. 35.
Allowable Subject Matter
Claims 3–11 and 13–19 allowed.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 C.F.R. § 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to § 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to DAVID P. ZARKA whose telephone number is (703) 756-5746. The Examiner can normally be reached Monday–Friday from 9:30AM–6PM ET.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Vivek Srivastava, can be reached at (571) 272-7304. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID P ZARKA/PATENT EXAMINER, Art Unit 2449