DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-16, in the reply filed on 06/26/2026 is acknowledged.
Claims 17-52 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to several distinct nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/26/2026.
Claim Objections
Claims 1, 3 and 7 are objected to because of the following informalities: each of these claims disclose a version of the phrase “the plurality of second circuit patterns are alternately and repeatedly arranged” (emphasis added). This appears to be incorrect word choice. The word “alternately” implies selection of one over another, whereas it seems likely that the applicant really intends “alternatingly”, such that there is one and then the other in a repetitive manner. Appropriate correction is required.
Claim 4 is objected to because of the following informalities: “the one first circuit pattern has grooves on lower sides of both side surfaces of the one first circuit pattern, and the one second circuit pattern has protrusions on lower sides of both side surfaces of the one second circuit pattern” (emphasis added). It is evident that the claimed structures are not imaginary two-dimensional structures and therefore should have more than two side surfaces (i.e. “both side surfaces”). Additionally, the limitation of “both side surfaces” lacks antecedent basis. However, these issues do not rise to the level of indefiniteness, as it seems clear that what is intended is actually: “the one first circuit pattern has grooves on lower sides of two side surfaces of the one first circuit pattern, and the one second circuit pattern has protrusions on lower sides of two side surfaces of the one second circuit pattern”. It is also likely that the Applicant may have intended: “the one first circuit pattern has grooves on lower sides of two opposing side surfaces of the one first circuit pattern, and the one second circuit pattern has protrusions on lower sides of two opposing side surfaces of the one second circuit pattern”; however, this interpretation would require improper importation of limitations from the specification into the claims. If the second interpretation is more in line with that which was intended by the Applicant, then they are strongly encouraged to amend the claim accordingly.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 discloses “at least one of the plurality of first circuit patterns and at least one of the plurality of second circuit patterns are alternately and repeatedly arranged” (lines 9-11; emphasis added). This limitation makes no logical sense. The phrase “at least one” includes a reasonable interpretation of “only one”. As such, with respect to the claimed arrangement there can be only one first circuit pattern and only one second circuit pattern. In this reasonable interpretation the one first circuit pattern and one second circuit pattern cannot be “repeatedly arranged” because they do not repeat. Accordingly, there are two reasonable interpretations of this limitation, either: 1. The one first circuit pattern and one second circuit pattern are not repeatedly arranged at all; or 2. The first circuit pattern and second circuit pattern must actually be at least two of each, and then they can in fact be alternately and repeatedly arranged.
Claims 2-16 are also rejected as indefinite, so rendered by virtue of their dependency upon the indefinite subject matter of claim 1.
Claim 3 is further rejected as indefinite, because the claim discloses “one first circuit pattern among the plurality of first circuit patterns and one second circuit pattern among the plurality of second circuit patterns are alternately and repeatedly arranged” (lines 1-5; emphasis added). This claim is indefinite for the same reasons as claim 1, except that it is even more indefinite, because it explicitly limits the number of each type of pattern to “one” and therefore being “repeatedly arranged” is a literal impossibility. This claim is further found to be indefinite, because aside from making the claims more indefinite, it is not understood to further limit the printed circuit board of claim 1 in any discernable manner. As such, it is impossible to ascertain the scope or metes and bounds of the claim.
Claim 5 is further rejected as indefinite, because the claim discloses “a line width of the one first circuit pattern, a line width of the one second circuit pattern, and an interval between the one first circuit pattern and the one second circuit pattern are substantially equal to each other” (lines 1-5; emphasis added). Though the Applicant has made an apparent attempt at defining the term “substantially” in the specification (par. 0149), this purported definition does nothing to actually clarify this relative term. There is no industry standard for, nor is there any further explanation in the original disclosure of what is or is not considered to fall within the realm of being “substantially equal”. Even if the specification uses the same term of degree as in the claim, a rejection is proper if the scope of the term is not understood when read in light of the specification. While, as a general proposition, broadening modifiers are standard tools in claim drafting in order to avoid reliance on the doctrine of equivalents in infringement actions, when the scope of the claim is unclear a rejection under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, is proper. See MPEP 2173.05(b): Relative Terminology. Is a measurement of 51% considered close enough to be substantially equal? What about 75% or 90% or 95%? The specification states that: “having substantially the same line width/thickness may include not only a case of being completely numerically identical, but also a case of having substantially similar numerical values within an error range. In addition, being substantially coplanar may include not only a case of being completely in the same plane, but also a case of being in approximately the same plane.” (par. 0150). This is not a further definition, especially given that the term “substantially” is being defined paradoxically using the term “substantially” as well as other hedging terms: “similar” and “approximately” which mean nothing more than substantially and do nothing to clarify the situation. Accordingly, the scope or metes and bounds of the claim are found to be ambiguous and thereby are held to be indefinite.
Claims 8 and 10 are rejected as indefinite for effectively the same reasons as claim 5. One cannot possibly know what does or does not satisfy being “inclined to substantially reduce an interval between the one side surfaces toward the first insulating layer” (claim 8), or “an interval between the pair of first circuit patterns are substantially equal to each other” (claim 10).
Claim 8 is further rejected as indefinite, because the claim discloses “one side surfaces of the pair of first circuit patterns, facing each other, are inclined to substantially reduce an interval between the one side surfaces toward the first insulating layer” (lines 1-4; emphasis added). This claim is replete with errors and is essentially impossible to understand. First, there are significant inconsistencies in the numerical references in the claim. It is impossible for “one” to refer to “surfaces” (plural). It is also impossible for “one side surface” to be “facing each other”. Further, it is impossible for static and immobile objects (e.g. one or more “side surface”) to reduce anything, including a distance therebetween. The interval is static and cannot be reduced by simply having an angled face. This is not how reduction or intervals of static objects work. Perhaps the intent is to disclose that the interval between two side surfaces is less at one location than at another location based upon the inclined surfaces relative angles, but this is not what was claimed, and it would be improper to read such significant limitation into the claim. If that was the intent, then the Applicant is encouraged to determine if there is support for such a limitation and if so, amend the claim accordingly.
Claim 9 is further rejected as indefinite, because the claim discloses “in the cross-sectional view, the pair of first circuit patterns have grooves on lower sides of the other side surfaces of the pair of first circuit patterns, and the one second circuit pattern has protrusions on lower sides of both side surfaces of the one second circuit pattern.” (lines 1-7; emphasis added). There is a lack of antecedent basis for the italicized limitations in the claim, and it is not clear if they were previously inadvertently omitted in claims 1, 7 or 8, or if they are intended to be new limitations.
Claim 10 is further rejected as indefinite, because the claim discloses “a line width of each of the pair of first circuit patterns, a line width of the one second circuit pattern, an interval between each of the pair of first circuit patterns and the one second circuit pattern, and an interval between the pair of first circuit patterns are substantially equal to each other” (lines 1-7; emphasis added). The run-on nature of this claim renders it indefinite as it is quite difficult to determine what width(s) and/or interval(s) is/are being measured/compared. Further, it is impossible to know how one measures a single interval between “each of the pair of first circuit patterns and the one second circuit pattern”. This is because there are three objects listed and as such there should be two intervals, not one.
Claim 12 is further rejected as indefinite, because the claim discloses “the protruding portion of the first insulating layer has a step difference with a different portion of the first insulating layer disposed between the one side surfaces of the pair of first circuit patterns” (lines 2-5; emphasis added). The phrase “a step difference” is not an industry standard term and carries no obvious meaning. It is impossible to know what a “step difference” is without reading limitations into the claim. Further, “a different portion” is impossible to understand as there was no previous disclosure of “a portion” and so one cannot possibly guess what element(s) is/are considered to be “a different portion”.
Claim 16 is further rejected as indefinite, because the claim discloses “The printed circuit board of claim 15, wherein a depth of the second opening is deeper than a depth of the first opening” (lines 1-3; emphasis added). This claim is indefinite because it depends from claim 15 which clearly discloses that the first opening and the second opening are not both required. There are effectively three reasonable interpretations of claim 15: 1 A first opening only; 2 A second opening only; or 3 Both a first and a second opening. For claim 16 to be definite, it must be enabled and understandable for all reasonable interpretations of the claims upon which it depends. This is not the case for either of the first two interpretations and therefore the scope or metes and bounds of the claim cannot be ascertained.
NOTE: All of the examined claims (i.e. claims 1-16) have been interpreted and examined as best understood according to the 112(b) rejections, above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nitta et al. (US 2021/0219424 A1).
Regarding claim 1, Nitta discloses a printed circuit board (10) (fig. 7: all) comprising: a first insulating layer (3) (pars. 0042-0044); *a plurality of first circuit patterns (25, including: 25a, 25b) respectively disposed on the first insulating layer; and a plurality of second circuit patterns (23, including: 23a, 23b) respectively disposed on the first insulating layer and respectively having a thickness (H11), thinner than a thickness (H21) of each of the plurality of first circuit patterns, wherein at least one of the plurality of first circuit patterns and at least one of the plurality of second circuit patterns are alternately and repeatedly arranged (fig. 7: there are two of 25, and then adjacent to the two of 25, alternately, there are two of 23; the presence of two of each satisfy the repeatedly limitation as well) (pars. 0112-0117).
*NOTE: regarding the various instances throughout the claims of “a plurality of first circuit patterns”, “a plurality of second circuit patterns”, “third circuit patterns”, etc., the claims do not currently define what differentiates a “first” pattern from a “second” pattern and so forth. As such, the reader is left to subjectively decide what constitutes these “patterns” and what may or may not differentiate them from one another. If the Applicant wishes for the, e.g. first and second circuit patterns to be distinct from one another in some manner, then they are strongly encouraged to claim as much.
Regarding claim 2, Nitta discloses the printed circuit board of claim 1, wherein a line width (L21) of each of the plurality of first circuit patterns and a line width (L11) of each of the plurality of second circuit patterns is 10 µm or less, respectively, and an interval (S21 for first circuit patterns and S11 for the second circuit patterns) between each of the plurality of first circuit patterns and each of the plurality of second circuit patterns is each 10 µm or less (fig. 7; pars. 0115, 0057, 0059, 0067 and 0069-0071).
Regarding claim 3, Nitta discloses the printed circuit board of claim 1, wherein one first circuit pattern among the plurality of first circuit patterns and one second circuit pattern among the plurality of second circuit patterns are alternately and repeatedly arranged (fig. 7).
Regarding claim 7, Nitta discloses the printed circuit board of claim 1, wherein a pair of first circuit patterns among the plurality of first circuit patterns and one second circuit pattern among the plurality of second circuit patterns are alternately and repeatedly arranged (fig. 7).
Claims 1 and 3-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 10,076,038 B2).
Regarding claim 1, Park discloses a printed circuit board (fig. 2: 1000) comprising: a first insulating layer (110); *a plurality (two) of first circuit patterns (52, 220) respectively disposed on the first insulating layer (fig. 2; col. 2, lines 15-26; col. 3, lines 14-34); and a plurality (two) of second circuit patterns (55) respectively disposed on the first insulating layer and respectively having a thickness (vertical double ended arrow in annotated fig. 2, below), thinner than a thickness (other vertical double ended arrow in annotated fig. 2, below) of each of the plurality of first circuit patterns (fig. 2; col. 3, lines 19-34), wherein at least one of the plurality of first circuit patterns and at least one of the plurality of second circuit patterns are alternately and repeatedly arranged (fig. 2: there are two of 52/220, and then adjacent to the two of 52/220, alternately, there are two of 55; the presence of two of each satisfy the repeatedly limitation as well) (cols. 3-4, lines 58-67 and 1-3).
PNG
media_image1.png
600
940
media_image1.png
Greyscale
Regarding claim 3, Park discloses the printed circuit board of claim 1, wherein one first circuit pattern among the plurality of first circuit patterns and one second circuit pattern among the plurality of second circuit patterns are alternately and repeatedly arranged (see claim 1 and fig. 2).
Regarding claim 4, Park discloses the printed circuit board of claim 3, wherein, in a cross-sectional view, the one first circuit pattern has *grooves (interior corner between 52 and 220) on lower sides of both side surfaces of the one first circuit pattern, and the one second circuit pattern has protrusions (in layer 300) on lower sides of both side surfaces of the one second circuit pattern (fig. 2).
*NOTE: the term “grooves” may not have been used by the applicant in a manner consistent with common usage of the word. As such, and because the Applicant is permitted to act as their own lexicographer, the term is being interpreted to include the standard definition of “grooves” and to include any indentation or simple rounded or chamfered corners (see, e.g., fig. 5, element 121U).
Regarding claim 5, Park discloses the printed circuit board of claim 4, wherein a line width of the one first circuit pattern, a line width of the one second circuit pattern, and an interval between the one first circuit pattern and the one second circuit pattern are substantially equal to each other (horizontal double ended arrows: annotated fig. 2, above).
Regarding claim 6, Park discloses the printed circuit board of claim 4, wherein a portion of the first insulating layer is disposed to protrude between at least one of one side surface or the other side surface of the one first circuit pattern and at least one of one side surface or the other side surface of the one second circuit pattern (fig. 2).
Regarding claim 7, Park discloses the printed circuit board of claim 1, wherein a pair of first circuit patterns among the plurality of first circuit patterns and one second circuit pattern among the plurality of second circuit patterns are alternately and repeatedly arranged (fig. 2).
Regarding claim 8, Park discloses the printed circuit board of claim 7, wherein one side surfaces (side surface(s) of 52) of the pair of first circuit patterns, facing each other, are inclined to substantially reduce an interval (the interval narrows toward the bottom, as viewed) between the one side surfaces toward the first insulating layer (fig. 2).
Regarding claim 9, Park discloses the printed circuit board of claim 8, wherein, in the cross-sectional view, the pair of first circuit patterns have *grooves (interior corner between 52 and 220) on lower sides of the other side surfaces of the pair of first circuit patterns, and the one second circuit pattern has protrusions (in layer 200) on lower sides of both side surfaces of the one second circuit pattern (fig. 2).
*NOTE: Please refer to the note below claim 4, above.
Regarding claim 10, Park discloses the printed circuit board of claim 9, wherein a line width of each of the pair of first circuit patterns, a line width of the one second circuit pattern, an interval between each of the pair of first circuit patterns and the one second circuit pattern, and an interval between the pair of first circuit patterns are substantially equal to each other (horizontal double ended arrows: annotated fig. 2, above).
Regarding claim 11, Park discloses the printed circuit board of claim 9, wherein a portion of the first insulating layer is disposed to protrude between at least one of the other side surfaces of the pair of first circuit patterns and at least one of one side surface or the other side surface of the one second circuit pattern (fig. 2).
Regarding claim 12, Park discloses the printed circuit board of claim 11, wherein the protruding portion of the first insulating layer has a step difference with a different portion of the first insulating layer disposed between the one side surfaces of the pair of first circuit patterns (fig. 2).
Regarding claim 13, Park discloses the printed circuit board of claim 1, further comprising: at least one third circuit pattern (410) disposed on the first insulating layer and having a width or a line width, respectively wider than a line width of each of the plurality of first circuit patterns and a line width of each of the plurality of second circuit patterns (fig. 2: each of 410 is wider than 52, 55 and 220); and at least one fourth circuit pattern (230) disposed on the first insulating layer, having a thickness (vertically), thinner than a thickness of the at least one third circuit pattern (230 is thinner than 410), and having a width or a line width, respectively wider than the line width of each of the plurality of first circuit patterns and the line width of each of the plurality of second circuit patterns (230 is wider than 52, 55 and 220) (fig. 2).
Claims 1-2 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu et al. (US 2015/0357276 A1).
Regarding claim 1, Shimizu discloses a printed circuit board (70) comprising: a first insulating layer (12); a plurality (four) of first circuit patterns (54) respectively disposed on the first insulating layer; and a plurality (fifteen) of second circuit patterns (64) respectively disposed on the first insulating layer and respectively having a thickness, thinner than a thickness of each of the plurality of first circuit patterns (fig. 4: each of 64 is thinner than each of 54), wherein at least one of the plurality of first circuit patterns and at least one of the plurality of second circuit patterns are alternately and repeatedly arranged (fig. 4; pars. 0045-0048).
Regarding claim 2, Shimizu discloses the printed circuit board of claim 1, wherein a line width of each of the plurality of first circuit patterns and a line width of each of the plurality of second circuit patterns is 10 µm or less, respectively, and an interval between each of the plurality of first circuit patterns and each of the plurality of second circuit patterns is each 10 µm or less (fig. 4; par. 0048).
Regarding claim 13, Shimizu discloses the printed circuit board of claim 1, further comprising: at least one third circuit pattern (212, 214) disposed on the first insulating layer and having a width or a line width, respectively wider than a line width of each of the plurality of first circuit patterns and a line width of each of the plurality of second circuit patterns; and at least one fourth circuit pattern (58, 230) disposed on the first insulating layer, having a thickness, thinner than a thickness of the at least one third circuit pattern, and having a width or a line width, respectively wider than the line width of each of the plurality of first circuit patterns and the line width of each of the plurality of second circuit patterns (figs. 4 and 21: 212/214 and 58/230 are both wider than 53 and 54 and 212/214 is thicker than 58/230; pars. 0036, 0050-0051, 0171 and 0176-0177).
Regarding claim 14, Shimizu discloses the printed circuit board of claim 13, further comprising: a first wiring layer disposed on an *upper surface of the first insulating layer, and including the plurality of first circuit patterns, the plurality of second circuit patterns, and the at least one third circuit pattern (the claimed “first wiring layer” is simply a re-naming of the first, second and third circuit patterns); a second wiring layer (44) disposed on a lower surface of the first insulating layer, and including a plurality of fifth circuit patterns (this is simply a re-naming of the second wiring layer) having a width or a line width, respectively wider than the line width of each of the plurality of first circuit patterns and the line width of each of the plurality of second circuit patterns; a first connection via (52) passing through the first insulating layer and connected to at least a portion of the second wiring layer; a second insulating layer disposed (35) on the lower surface of the first insulating layer and covering at least a portion of the second wiring layer; a third wiring layer (46, 86) disposed on a lower surface of the second insulating layer and including a plurality of sixth circuit patterns having a width or a line width, respectively wider than the line width of each of the plurality of first circuit patterns and the line width of each of the plurality of second circuit patterns (fig. 21; pars. 0074-0078); and a second connection via (36) passing through the second insulating layer and connected to at least a portion of the third wiring layer (figs. 4 and 21: all of the circuit patterns, circuit layers and vias in this claim are connected to one another; pars. 0037-0042 and 0046-0049).
*NOTE: the relative directional terms, such as “upper”, “lower” and the like are subjectively defined and do not have referential directions provided in the claim. As such, so long as the interpreted subjective definition of each term is consistent (e.g. “lower” always means the same direction as viewed in the prior art), the term can be held to mean above or below.
Regarding claim 15, Shimizu discloses the printed circuit board of claim 14, further comprising: a first resist layer (215) disposed on the upper surface of the first insulating layer, covering at least a portion of the first wiring layer, and having at least one of a first opening (portion containing 213) exposing at least a portion of at least one of the at least one third circuit pattern (fig. 21), or a second opening (215X) exposing at least a portion of at least one of the at least one fourth circuit pattern; and a second resist layer (13) disposed on the lower surface of the second insulating layer, covering at least a portion of the third wiring layer, and having a third opening (13X) exposing at least a portion of at least one of the plurality of sixth circuit patterns (fig. 21; pars. 0073-0075).
Regarding claim 16, Shimizu discloses the printed circuit board of claim 15, wherein a depth (measured left-to-right) of the second opening is deeper than a depth of the first opening (fig. 21).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the concurrently mailed PTO-892, as all of those cited references are considered to be pertinent to the claimed invention. For example, Lin et al. (US 20190380211 A1) is held to disclose most, if not all, of the limitations of at least claim 1. Lin discloses a printed circuit board (fig. 1F: all) with a first insulated layer (100’/220), having first circuit patterns (211) and second circuit patterns (110); wherein the first circuit patterns are thicker than the second circuit patterns (fig. 1F; par.0030). The Lin reference is not currently applied as an anticipation rejection due to the completeness of the above applied art, and in order to avoid an overly long Office Action or duplicative rejections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey T Carley whose telephone number is (571)270-5609. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sunil Singh can be reached at (571)272-3460. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
Prosecution Insights