Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The IDS dated 5/22/2024 contains a citation for an International Search Report and Written Opinion, but no such document is of record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-14 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Long et al., US PGPub 2016/0321200, in view of Nochimowski et al., US PGPub 2009/0172276, further in view of Tang et al., US Patent 7,657,823.
With respect to claim 1, Long teaches a storage system, comprising:
a plurality of data storage devices (par. 12, storage sleds 110), wherein:
each data storage device of the plurality of data storage devices is coupled to another data storage device of the plurality of data storage devices (pars. 12-13, the storage sleds are coupled to each other via PCIe interface and sideband communication interfaces);
each data storage device comprises:
an end point (EP) peripheral component interconnect (PCI) express (PCIe) interface (par. 12, PCIe interface);
a serial bus (SMB) (par. 13, Universal Serial Bus); and
a high speed serial trace port (HSSTP) interface, wherein the HSSTP interface comprises:
a PCIe transmitter (TX) (par. 14, PCIe switch 115);
a universal asynchronous receiver-transmitter (UART) receiver (RX) (par. 13, UART receiver); and
a UART TX (par. 13, UART transmitter); and
a first data storage device is configured to send data via the PCIe TX of the first data storage device to the EP PCIe interface of a second data storage device (par. 14, storage sleds transfer data over a common PCIe interface shared by each SSD), wherein:
the first data storage device is coupled to the second data storage device (pars. 12-13, the storage sleds are coupled to each other via PCIe interface and sideband communication interfaces);
Long fails to teach the sending occurs after a predetermined amount of data that is less than all of the data has been programmed to the first data storage device. Nochimowski teaches:
a first data storage device of the plurality of data storage devices is configured to generate a write command for each of the other data storage devices of the plurality of data storage devices and send data and the write command to the second data storage device (pars. 58-59 and fig. 5, the real sectors in storage region 540 are the first data storage device, to which a write command data is issued, the cache 558 is the second storage device, which receives the write command and data), wherein:
the first data storage device is coupled to the second data storage device (pars. 53-54 and 58, the cache 558 is coupled to the real sectors, either in the same storage region 540, or alternatively, located in RAM outside of the storage array);
the sending occurs after a predetermined amount of data that is less than all of the data has been programmed to the first data storage device (pars. 58-59, data is written to the real sectors in real time, while data is sent to the cache);
the second data storage device is configured to send the write command and the data to the at least one of the other data storage devices of the plurality of data storage devices (pars. 58-59 and fig. 5, the write command 513 and the data are forwarded to external device 522).
Long and Nochimowski fail to teach the first and second storage devices generating ECC data for the stored data.
Tang teaches:
the data is programmed to the second storage device (col. 2, lines 13-15, two drives each containing the same information);
the first and second data storage devices are configured to generate their own error correction code (ECC) data for the data (col. 1, lines 46-49, each drive in the RAID system generates its own ECC data).
It would have been obvious to one of ordinary skill in the art, having the teachings of Long and Nochimowski l before him before the earliest effective filing date, to modify the data storage system of Long with the data storage system of Nochimowski, as it is more efficient to wait until a predetermined quantity of data is cached before forwarding a write command to an external device, as taught by Nochimowski in par. 58. Further, it would have been obvious, also having the teachings of Tang before him before the earliest effective filing date, to modify the data storage system of Long and Nochimowski with data storage system of Tang, in order to handle drive failures, as taught by Tang in col. 1, lines 37-49.
With respect to claim 2, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 1, wherein sending data via the PCIe TX of the first data storage device to the EP PCIe interface of the second data storage device occurs over a high speed data path (pars. 12-13, the PCIe interface is a high speed data path compared to the sideband communication interfaces such as the UART and USB interfaces).
With respect to claim 3, Long, Nochimowski and Tang teach the limitations of the parent claim. Nochimowski further teaches the storage system of claim 2, wherein the high speed data path is unidirectional, and wherein the high speed data path is a TX path (par. 53 and fig. 5, the communication path 556 is shown as unidirectional and used to transfer data and commands).
With respect to claim 4, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 2, wherein the high speed data path is dual-directional, wherein the high speed data path is configured to switch from a TX path to an RX path and from the RX path to the TX path (pars. 12-13 and fig. 1, the PCIe fabric is used to transfer data in both directions between the storage sleds and processing modules).
With respect to claim 5, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 4, wherein a control message controlling the switching is communicated through the high speed data path (par. 30, the PCIe switch fabric is used to control receiving and transmitting to and from any of the storage sleds).
With respect to claim 6, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 4, wherein a control message controlling the switching is communicated over the UART RX and the UART TX of adjacent data storage devices (pars. 31-32 and fig. 1, the UART RX and TX paths are used to perform the initialization process before the storage operations can be handled. Par. 32 describes that the UART interface may be shared among the device which branch off a common link, and therefore is communicated over the UART RX and UART TX of adjacent storage devices).
With respect to claim 7, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 4, wherein the switching a control message controlling the switching is communicated over the SMB of adjacent data storage devices (pars. 31-32 and fig. 1, the USB interface may be used to perform the initialization process before the storage operations can be handled. Par. 32 describes that the sideband interface may be shared among the device which branch off a common link, and therefore is communicated over the USB interface of adjacent storage devices).
With respect to claim 8, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 2, wherein the second data storage device is configured to send data back to the first data storage device via a low speed data path coupling the UART TX of the second data storage device to the UART RX of the first data storage device, and wherein the low speed data path has a slower data transfer speed than the high speed data path (par. 23, the UART interface is shared among the storage devices, UART having slower data transfer speed than PCIe, the high speed data path of the claims).
With respect to claim 9, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 1, wherein the first data storage device is coupled to a host device, and wherein the first data storage device is further configured to: receive the data from the host device via a data path coupling a root complex (RC) PCIe interface of the host device to the EP PCIe interface of the first data storage device; and cause the data to be transferred to each of the other data storage devices of the plurality of the data storage devices to be programmed (par. 30, the PCIe switch fabric is the root complex, and is used to control receiving and transmitting data to and from any of the storage sleds).
With respect to claim 10, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 1, wherein the data is programmed to two or more data storage devices of the plurality of data storage devices concurrently (pars. 36-37, the control modules can send initialization messages to the storage sleds concurrently).
With respect to claim 11, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 1, wherein the first data storage device is further coupled to at least another data storage device other than the second data storage device (par. 14, the storage sleds are connected over a common PCIe interface).
With respect to claim 12, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 1, wherein each data storage device of the plurality of data storage devices are configured to communicate with each other data storage device of the plurality of data storage devices via the SMB (par. 27 and fig. 1, the USB hub has a fan out interface connected to the USB interfaces 114 of each storage sled for communication).
With respect to claim 13, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 1, wherein at least one data storage device of the plurality of data storage devices comprises a second EP PCIe interface (par. 13, the storage sleds communicate redundantly over two PCIe interfaces).
With respect to claim 14, Long teaches a storage system, comprising:
a first data storage device (par. 12 and fig. 1, the first of the storage sleds 110); and
a second data storage device coupled to the first data storage device (par. 12 and fig. 1, a second one of storage sleds 110), wherein the first data storage device is configured to:
program data to a non-volatile memory (NVM) device of the first data storage device (pars. 56-59 and fig. 3, reads and writes are directed towards the storage sleds. Par. 14 discloses that the storage sleds contain non-volatile memory, particularly an SSD) ;
generate a write command for the second data storage device to program the data to an NVM device of the second data storage device (par. 58 and fig. 3, a write operation is directed to a storage sled); and
send the data to the second data storage device via a high speed data path coupling the first data storage device to the second data storage device (par. 58 and fig. 3, the write is sent over the PCIe fabric, the high speed data path), wherein:
the high speed data path is distinct from a low speed data path (pars 48-49 and fig. 3, the sideband links 346 and 347 are the low speed data path);
the low speed data path has a data transfer speed less than the high speed data path (pars. 50 and 58, where the sideband links are UART and the high speed data path is PCIe, UART having a lower speed than PCIe);
the high speed data path is utilized to transfer write data (par. 58, the write occurs over PCIe); and
the low speed data path is utilized to transfer read data (pars. 49-50, the sideband links are used for reading and writing between data storage sleds);
Long fails to teach the sending occurs after a predetermined amount of data that is less than all of the data has been programmed to the NVM device of the first data storage device and wherein programming the data to the NVM device of the second data storage device occurs partially concurrently with programming the data to the NVM device of the first data storage device.
Nochimowski teaches:
one or more data storage devices coupled to the second data storage device or another data storage device of the one or more other data storage devices (pars. 58-59 and fig. 5, the real sectors in storage region 540 are the first data storage device, the cache 558 is the second storage device, and external device 522 is the one or more other data storage devices)
send the data and the write command to the second data storage device via a high speed data path coupling the first data storage device to the second data storage device after a predetermined amount of the data has been programmed to the NVM device of the first data storage device, wherein the second data storage device is configured to: receive the data from the first data storage device; and program the data to the NVM device of the second data storage device, wherein programming the data to the NVM device of the second data storage device occurs partially concurrently with programming the data to the NVM device of the first data storage device (pars. 58-59 and fig. 5, the real sectors in storage region 540 are the first data storage device, to which a write command data is issued, the cache 558 is the second storage device, which receives the write command and data, and data is written to the real sectors in real time, while data is sent to the cache); and
send the write command and the data to at least one of the one or more other data storage device (pars. 58-59 and fig. 5, the write command 513 and the data are forwarded to external device 522).
Long and Nochimowski fail to teach the first and second storage devices generating ECC data for the stored data.
Tang teaches:
wherein the first and second data storage devices are configured to generate their own error correction code (ECC) data for the data (col. 1, lines 46-49, each drive in the RAID system generates its own ECC data).
It would have been obvious to one of ordinary skill in the art, having the teachings of Long and Nochimowski l before him before the earliest effective filing date, to modify the data storage system of Long with the data storage system of Nochimowski, as it is more efficient to wait until a predetermined quantity of data is cached before forwarding a write command to an external device, as taught by Nochimowski in par. 58. Further, it would have been obvious, also having the teachings of Tang before him before the earliest effective filing date, to modify the data storage system of Long and Nochimowski with data storage system of Tang, in order to handle drive failures, as taught by Tang in col. 1, lines 37-49.
With respect to claim 18, Long, Nochimowski and Tang teach the limitations of the parent claim. Long further teaches the storage system of claim 14, wherein the low speed data path is further utilized to transfer control data (pars. 49-50, control module 325 initializes the data storage sleds using the sideband links 346 and 347).
With respect to claim 19, Long teaches a storage system, comprising:
a first data storage device (par. 46 and fig. 3, a first one of the storage sleds 310);
a second data storage device coupled to the first data storage device (par. 46 and fig. 3, a second one of storage sleds 310);
means for transferring write data from the first data storage device to the second data storage device (pars. 46-47 and fig. 3, the PCIe switches 321 and links 340 for transferring data between storage sleds); and
means for transferring control data between the first data storage device and the second data storage device, wherein the means for transferring write data is distinct from the means for transferring control data (par. 49 and fig. 3, the sideband links 346 and 347 for communicating data between the storage sleds).
the first data storage device is configured to:
receive data from a host device to program to a memory device of the first data storage device (par. 57-58, receiving data from a processing module (host) for a write to a storage sled);
program the data to the memory device of the first data storage device (pars. 57-58 a write to a storage sled);
generate a command for the second data storage device to program the data to a memory device of the second data storage device (par. 58, a write operation for a write to another storage sled); and
send the data and the generated command to the second data storage device device (par. 58, a write operation for the storage sled from a processing module);
Long teaches transferring control data between the storage devices, but doesn’t explicitly disclose transferring read data on the sideband links. Long also fails to teach to program the data to the memory device of the second data storage device, wherein programming the data to the memory device of the second data storage device occurs partially concurrently to programming the data to the memory device of the first data storage device.
Nochimowski teaches:
one or more other data storage devices coupled to the second data storage device or another data storage device of the one or more other data storage devices (pars. 58-59 and fig. 5, the real sectors in storage region 540 are the first data storage device, the cache 558 is the second storage device, and external device 522 is the one or more other data storage devices)
means for transferring read data between the first data storage device and the second data storage device, wherein the means for transferring write data is distinct from the means for transferring read data (par. 53 and fig. 5, write data is cached in cache 558 on LSD 504 before sending to external device 522, which is distinct from the path 556 used for read commands to the host device 502).
the second storage device is configured to:
program the data to the memory device of the second data storage device, wherein programming the data to the memory device of the second data storage device occurs partially concurrently to programming the data to the memory device of the first data storage device (pars. 58-59 and fig. 5, the real sectors in storage region 540 are the first data storage device, to which a write command data is issued, the cache 558 is the second storage device, which receives the write command and data, and data is written to the real sectors in real time, while data is sent to the cache); and
send the generated command the data to at least one of the one or more other data storage device (pars. 58-59 and fig. 5, the write command 513 and the data are forwarded to external device 522)
Long and Nochimowski fail to teach the first and second storage devices generating ECC data for the stored data.
Tang teaches:
wherein the first and second data storage devices are configured to generate their own error correction code (ECC) data for the data (col. 1, lines 46-49, each drive in the RAID system generates its own ECC data).
It would have been obvious to one of ordinary skill in the art, having the teachings of Long and Nochimowski l before him before the earliest effective filing date, to modify the data storage system of Long with the data storage system of Nochimowski, as it is more efficient to wait until a predetermined quantity of data is cached before forwarding a write command to an external device, as taught by Nochimowski in par. 58. Further, it would have been obvious, also having the teachings of Tang before him before the earliest effective filing date, to modify the data storage system of Long and Nochimowski with data storage system of Tang, in order to handle drive failures, as taught by Tang in col. 1, lines 37-49.
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Long, Nochimowski and Tang as applied to claim 14 above, and further in view of Numura et al., US PGPub 2018/0039441.
With respect to claim 15, Long, Nochimowski and Tang teach the limitations of the parent claim. Numura further teaches the storage system of claim 14, wherein:
first error correction code (ECC) is generated by the first data storage device for the data programmed to the NVM device of the first data storage device and programmed and to the NVM device of the first data storage device (par. 184, a portion of the error correction code is distributed to SSD 400); and
second ECC is generated by the second data storage device for the data programmed to the NVM device of the second data storage device and programmed and to the NVM device of the second data storage device (par. 184, a portion of the error correction code is distributed to SSD 401).
It would have been obvious to one of ordinary skill in the art, having the teachings of Long, Nochimowski, Tang and Numura before him before the earliest effective filing date, to modify the data storage system of Long, Nochimowski and Tang with the data storage system of Numura, in order to efficiently distribute data and detect and correct errors among a plurality of solid-state storage devices, as taught by Numura in par. 4.
With respect to claim 16, Long, Nochimowski, Tang and Numura teach the limitations of the parent claim. Numura further teaches the storage system of claim 15, wherein the second data storage device is configured to request the first ECC from the first data storage device to correct the data programmed to the NVM device of the second data storage device (par. 51 and fig. 1, a storage control device 100 acquires an error correction code from another SSD different from the SSD which stores a portion of the data requested to be read).
With respect to claim 17, Long, Nochimowski, Tang and Numura teach the limitations of the parent claim. Numura further teaches the storage system of claim 15, wherein the first data storage device is configured to request the data programmed to the NVM device of the second data storage device responsive to determining that the data programmed to the NVM of the first data storage device is corrupted (pars. 100-101, determining whether an SSD is in execution of GC).
Response to Arguments
Applicant's arguments filed 01/07/2026 have been fully considered but they are not persuasive. Firstly, the examiner would like to note that the International Search Report and Written Opinion listed in the 05/22/2024 IDS has still not been entered into record. Applicant’s arguments on pages 8-10, with respect to claims 1-14 and 18-19, are directed towards Long and Nochimowski failing to teach first and second storage devices being configured to generate their own error correction code (ECC) data for the data, as well as the storage regions configured to store the same data. These arguments are moot, as the new Tang reference teaches these limitations in col. 1, lines 46-49 and col. 2, lines 13-15, as discussed in the rejection above. Applicant’s arguments on pages 10-11, regarding dependent claims 15-17, are directed towards the limitations of parent claim 14, and are moot given the new rejection of claim 14.
Conclusion
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132