DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scott U.S. Patent No. 5,986,860 (hereinafter “Scott”).
Regarding claim 1, Scott teaches a system (refer to fig.3), comprising: an electrical load (implicit)(refer to col. 6 lines 37-64: “load ends”); load circuitry (i.e. resistors 62)(fig.3) coupled to the electrical load (implicit) and configured to output first data indicative of a first average of input load voltages across the electrical load (refer to col. 6 lines 37-64); a power source (i.e. power source in the figure below)(fig.3); and power source circuitry (i.e. resistors 52 and arc detector 70)(fig.3) coupled to the power source and the load circuitry (implicit), the power source circuitry configured to interrupt the power source (refer to col. 7 lines 31-46) based on the first data indicative of the first average of the input load voltages and second data indicative of a second average of power source bus voltages (refer to col. 6 lines 37-64 and col. 7 lines 31-46).
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Regarding claim 5, Scott teaches the system of claim 1, wherein the power source circuitry is configured to interrupt the power source based on an average voltage differential between the first average of the input load voltages and the second average of the power source bus voltages exceeding a threshold voltage differential (refer to col. 7 lines 31-46).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5, 9-12, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoepf et al. U.S. Patent Application 2004/0150410 (hereinafter “Schoepf”) and further in view of Luciani et al. U.S. Patent Application 2014/0268458 (hereinafter “Luciani”).
Regarding claim 1, Schoepf teaches a system (refer to fig.3), comprising: an electrical load (i.e. load in the figure below)(fig.3); load circuitry (i.e. load circuitry in the figure below)(fig.3) coupled to the electrical load (implicit) and configured to output first data indicative of a first component of input load voltages across the electrical load (refer to [0021]); a power source (i.e. battery in the figure below)(fig.3); and power source circuitry (i.e. smart connector 34)(fig.3) coupled to the power source and the load circuitry (implicit), the power source circuitry configured to interrupt the power source (refer to [0021]) based on the first data indicative of the first component of the input load voltages and second data indicative of a second component of power source bus voltages (refer to [0021] and abstract); however, Schoepf does not teach wherein the first component and the second component are a first average and a second average. However, Luciani teaches wherein the first component and the second component are a first average and a second average (refer to [0040]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Schoepf to replace the smart connectors 34 and 36 with the power protection devices 300 (fig.3) of Luciani to provide the advantage of averaging a series of voltage samples to reduce nuisance trips (refer to Luciani [0009]).
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Regarding claim 2, Schoepf and Luciani teach the system of claim 1, wherein the load circuitry is configured to transmit the first data indicative of the first average of the input load voltages to the power source circuitry via a Controller Area Network (CAN) link (refer to Schoepf [0031]).
Regarding claim 5, Schoepf and Luciani teach the system of claim 1, wherein the power source circuitry is configured to interrupt the power source based on an average voltage differential between the first average of the input load voltages and the second average of the power source bus voltages exceeding a threshold voltage differential (refer to Schoepf [0018], [0021], abstract, and claim 1)(refer also to Luciani [0009] and [0040]).
Regarding claim 19, Schoepf teaches an operation to determine a plurality of output voltages corresponding to a power source (refer to Schoepf [0018], [0021], abstract, and claim 1); determine a first component of the plurality of output voltages (refer to Schoepf [0018], [0021], abstract, and claim 1); determine a plurality of input voltages corresponding to a load coupled to the power source (refer to Schoepf [0018], [0021], abstract, and claim 1); determine a second component of the plurality of input voltages (refer to Schoepf [0018], [0021], abstract, and claim 1); and interrupt a flow of power from the power source to the load based on the first component of the plurality of output voltages and the second component of the plurality of input voltages (refer to Schoepf [0018], [0021], abstract, and claim 1); however, Schoepf does not teach a tangible, non-transitory, computer-readable medium, comprising instructions that, when executed by one or more processors, are configured to cause the one or more processors to: perform the operation; wherein the first component and the second component are a first average and a second average. However, Luciani teaches a tangible, non-transitory, computer-readable medium (refer to microprocessor 343)(fig.3), comprising instructions that, when executed by one or more processor (i.e. microprocessor 343)(fig.3)s, are configured to cause the one or more processors to: perform the operation (refer to microprocessor 343)(fig.3); wherein the first component and the second component are a first average and a second average (refer to [0040]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the operation of Schoepf to replace the smart connectors 34 and 36 with the power protection devices 300 (fig.3) of Luciani to provide the advantage of averaging a series of voltage samples to reduce nuisance trips (refer to Luciani [0009]).
Regarding claim 20, Schoepf and Luciani teach the tangible, non-transitory, computer readable medium of claim 19, wherein the instructions are configured to cause the one or more processors to interrupt the flow of power by opening a switch coupled to a power bus between the power source and the load (refer to Schoepf [0018], [0021], abstract, and claim 1)(refer also to Luciani [0009] and [0040]).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoepf and Luciani as applied to claim 1 above, and further in view of Hackner et al. German Patent Document DE 10 2017202538 A1 (hereinafter “Hackner”).
Regarding claim 3, Schoepf and Luciani teach the system of claim 1; however, they do not teach wherein the load circuitry is configured to transmit the first data indicative of the first average of the input load voltages to the power source circuitry via a Local Interconnect Network (LIN) link. However, Hackner teaches wherein the load circuitry is configured to transmit the first data indicative of the first average of the input load voltages to the power source circuitry via a Local Interconnect Network (LIN) link (refer to [0016]: “Particularly preferably, the further triggering signal can be transmitted via the bus system from the detection device to the evaluation device and / or the separating element. In this case, the bus system may be designed, for example, as a CAN bus or LIN bus or FlexRay or SPI or Ethernet.”). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Schoepf and Luciani to include the bus communication standard of Hackner to provide the advantage of using common, standardized bus communication techniques.
Regarding claim 4, Schoepf and Luciani teach the system of claim 1; however, they do not teach wherein the load circuitry is configured to transmit the first data indicative of the first average of the input load voltages to the power source circuitry via an Ethernet link. However, Hackner teaches wherein the load circuitry is configured to transmit the first data indicative of the first average of the input load voltages to the power source circuitry via an Ethernet link (refer to [0016]: “Particularly preferably, the further triggering signal can be transmitted via the bus system from the detection device to the evaluation device and / or the separating element. In this case, the bus system may be designed, for example, as a CAN bus or LIN bus or FlexRay or SPI or Ethernet.”). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Schoepf and Luciani to include the bus communication standard of Hackner to provide the advantage of using common, standardized bus communication techniques.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoepf and Luciani as applied to claim 5 above, and further in view of Aromin et al. U.S. Patent Application 2018/0151311 (hereinafter “Aromin”).
Regarding claim 6, Schoepf and Luciani teach the system of claim 5; however, they do not teach wherein the power source circuitry is configured to interrupt the power source based on the average voltage differential exceeding the threshold voltage differential for a number of samples greater than a threshold number of samples. However, Aromin teaches wherein the power source circuitry is configured to interrupt the power source based on the average voltage differential exceeding the threshold voltage differential for a number of samples greater than a threshold number of samples (refer to [0080]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Schoepf and Luciani to include the threshold number of samples of Aromin to provide the advantage of further reducing nuisance trips.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoepf and Luciani as applied to claim 5 above, and further in view of Potter et al. U.S. Patent Application 2022/0077671 (hereinafter “Potter”).
Regarding claim 7, Schoepf and Luciani teach the system of claim 5; however, they do not teach wherein the power source circuitry is configured to interrupt the power source based on the average voltage differential exceeding the threshold voltage differential for a period of time greater than a threshold period of time. However, Potter teaches wherein the power source circuitry is configured to interrupt the power source based on the average voltage differential exceeding the threshold voltage differential for a period of time greater than a threshold period of time (refer to [0025]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Schoepf and Luciani to include the threshold period of time of Potter to provide the advantage of further reducing nuisance trips.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 8 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 8, especially wherein the power source circuitry is configured to interrupt the power source based on determining that communication has been lost between the power source circuitry and the load circuitry for a period of time greater than a threshold period of time.
Claims 9-18 are allowed.
The following is an examiner’s statement of reasons for allowance: Claims 9-18 are allowable because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 9, especially a first microcontroller unit (MCU) coupled to the source voltage sensor and configured to output the first data; a second MCU coupled to the load voltage sensor and configured to cause a load power reduction based on the first data indicative of the first average of the output voltages and second data indicative of a second average of the input voltages. Regarding claim 9, Schoepf teaches an arc detection circuit (refer to fig.3 and abstract), comprising: a power bus (refer to positive wire 38)(fig.3); a power source (i.e. battery in the figure above)(fig.3) coupled to the power bus (implicit); power source circuitry (i.e. smart connector 34)(fig.3) coupled to the power source and the power bus (implicit), the power source circuitry comprising: a source voltage sensor (refer to Schoepf [0018], [0021], abstract, and claim 1)(refer also to Luciani [0009] and [0040]) configured to determine output voltages on the power bus (refer to Schoepf [0018], [0021], abstract, and claim 1); and a first unit coupled to the source voltage sensor (refer to [0031]) and configured to output first data indicative of a first component of the output voltages received from the source voltage sensor (refer to Schoepf [0018], [0021], abstract, and claim 1); an electrical load (i.e. load in the figure above)(fig.3) coupled to the power bus (implicit); and load circuitry (i.e. load circuitry in the figure above)(fig.3) coupled to the power bus and the electrical load (implicit), the load circuitry comprising: a load voltage sensor (refer to Schoepf [0018], [0021], abstract, and claim 1) configured to determine input voltages across the electrical load (refer to Schoepf [0018], [0021], abstract, and claim 1); however, Schoepf does not teach the first unit being a first microcontroller unit (MCU) coupled to the source voltage sensor and configured to output the first data; a second MCU coupled to the load voltage sensor and configured to cause a load power reduction based on the first data indicative of the first average of the output voltages and second data indicative of a second average of the input voltages. Luciani teaches a similar device (refer to fig.3); however Luciani does not teach a first microcontroller unit (MCU) coupled to the source voltage sensor and configured to output the first data; a second MCU coupled to the load voltage sensor and configured to cause a load power reduction based on the first data indicative of the first average of the output voltages and second data indicative of a second average of the input voltages. Claims 10-18 are allowed based on their dependency on claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838