DETAILED ACTION
Claims 21-39 are presented for examination. Applicant has cancelled claims 1-20 and added claims 21-39.
Examiner note: Applicant should update the related (parent) application with the latest status of the application (patent application number) in the specification.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 28-33 are objected to because of the following informalities: in claim 28 at line 5, after “and”, the “;” should be removed.
Claims 29-33 are objected due to its dependency on an objected claim.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 23-28, 30-34 and 38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-6, 9, 10, 12, 14, 16, 17, 21, 24 and 27 of U.S. Patent No. 11,748,172 B2.
Instant application
US 11,748,172 B2
Claim 21. An apparatus comprising:
an Ethernet network interface controller (NIC) located on a host compute device, the Ethernet NIC to include a first interface to communicatively couple with a host central processing unit (CPU) and a second interface to communicatively couple with a network of storage servers, wherein the Ethernet NIC also includes circuitry to:
obtain, from the host CPU, a request to access a data storage device; and
based on whether the data storage device is located on the host compute device or accessible through a storage server from among the network of storage servers, provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver.
Claim 1. An apparatus comprising:
an Ethernet network interface controller (NIC) located on a first compute device, the Ethernet NIC to include a central processing unit (CPU) interface to communicatively couple with a CPU and an Ethernet network
interface to communicatively couple to a network of compute devices, wherein the Ethernet NIC also includes a first circuitry to:
obtain, from a requestor device, a request to access a memory at a data storage device, wherein the data storage device does not include the Ethernet NIC;
(Claim 6. The apparatus of claim 5,) wherein to obtain the request to access the memory at the data storage device comprises to obtain the request from the CPU.
determine whether the data storage device is located on the first compute device or accessible through a second compute device from among the network of compute devices;
enable a non-volatile memory express driver; and provide, to the requestor device, access to the memory at the data storage device via use of the non-volatile memory express driver.
Claim 23. The apparatus of claim 21, wherein a data storage device map indicative of locations of a plurality of data storage devices is used to determine whether the data storage device is located on the host compute device or located on the storage server.
Claim 9. The apparatus of claim 1, wherein to determine whether the data storage device is located on the first compute device or located on the second compute device comprises to reference a data storage device map indicative of locations of a plurality of data storage devices.
Claim 24. The apparatus of claim 23, wherein the circuitry is to receive the data storage device map from an orchestrator server communicatively coupled to the circuitry.
Claim 3. The apparatus of claim 1, wherein the first circuitry is further to receive a map of data storage devices coupled to the network of compute devices from an orchestrator server
communicatively coupled to the first circuitry.
Claim 25. The apparatus of claim 21, the data storage device is located on the storage server, wherein the circuitry is further to:
cause the data storage device to be powered on at the storage server based on a request sent to a second circuitry of a second Ethernet NIC located at the storage server to power on the data storage device.
Claim 10. The apparatus of claim 1, the data storage device is determined to be located on the second compute device, wherein the first circuitry is further to:
cause the data storage device to be powered on at the second compute device based on a request sent to a second circuitry of a second Ethernet NIC located at the second compute device to power on the data storage
device.
Claim 26. The apparatus of claim 21, wherein the host CPU is to execute a workload on the host compute device.
Claim 5. The apparatus of claim 1, wherein the CPU is to execute a workload on the first compute device.
Claim 27. The apparatus of claim 21, the circuitry comprises a field-programmable gate array (FPGA).
Claim 4. The apparatus of claim 1, the first circuitry comprises a field-programmable gate array (FPGA).
Claim 28. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause circuitry of an Ethernet network interface controller (NIC) located on a host compute device to:
obtain, via a first interface coupled with a host central processing unit (CPU), a request from the host CPU to access a data storage device; and;
based on whether the data storage device is located on the host compute device or accessible through a storage server from among a network of storage servers coupled to the circuitry via a second interface, provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver.
Claim 12. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a system to:
obtain, with a first circuitry of an Ethernet network interface controller (NIC) located on a first compute device, the Ethernet NIC to include a central processing unit (CPU) interface coupled with a CPU and an
Ethernet network interface coupled to a network of compute devices, a request from a requestor device to access a memory at a data storage device, wherein the data storage device does not include the Ethernet NIC;
(Claim 17) wherein to obtain the request to access the memory at data storage device comprises to obtain the request from the CPU.
determine, with the first circuitry, whether the data storage device is located on the first compute device or accessible through a second compute device from among the
network of compute devices;
enable, with the first circuitry, a non-volatile memory express driver; and
provide, with the first circuitry and to the requestor device, access to the memory at the data storage device via use of the non-volatile memory express driver.
Claim 30. The one or more machine-readable storage media of claim 28, wherein a data storage device map indicative of locations of a plurality of data storage devices is used to determine whether the data storage device is located on the host compute device or located on the storage server.
Claim 20. The one or more machine-readable storage media of claim 12, wherein to determine whether the data storage device is located on the first compute device or located on the second compute device comprises to reference a data storage device map indicative of locations of a plurality of data storage devices.
Claim 31. The one or more machine-readable storage media of claim 30, wherein the plurality of instructions further cause the circuitry to receive the data storage device map from an orchestrator server communicatively coupled to the circuitry.
Claim 14. The one or more machine-readable storage media of claim 12, wherein the plurality of instructions further cause the system to receive, with the first circuitry, a map of data storage devices coupled to the network of compute devices from an orchestrator server communicatively coupled to the Ethernet NIC.
Claim 32. The one or more machine-readable storage media of claim 28, the data storage device is d located on the storage server, wherein the instructions are to further cause the circuitry to:
cause the data storage device to be powered on at the storage server based on a request sent, by the circuitry to a second circuitry of a second Ethernet NIC located at the storage server to power on the data storage device.
Claim 21. The one or more machine-readable storage media of claim 12, the data storage device is determined to be located on the second compute device, wherein the instructions are to further cause the system to:
cause the data storage device to be powered on at the second compute device based on a request sent, by the first circuitry to a second circuitry of a second Ethernet NIC located at the second compute device to power on
the data storage device.
Claim 33. The one or more machine-readable storage media of claim 28, wherein the host CPU is to execute a workload on the host compute device.
Claim 16. The one or more machine-readable storage media of claim 12, wherein the plurality of instructions further cause
the system to execute, with the CPU, a workload.
Claim 34. A method for accessing a data storage device, the method comprising:
obtaining, with circuitry of an Ethernet network interface controller (NIC) for a host computing device that includes a first interface to communicatively couple with a host central processing unit (CPU) and a second interface to communicatively couple to a network of storage servers, a request from the host CPU to access a data storage device; and
based on whether the data storage device is located on the host compute device or accessible through a storage server from among the network of storage servers, providing, by the circuitry, access to the data storage device by the host CPU via use of a non-volatile memory express driver.
Claim 24. A method for accessing a data storage device, the method comprising:
obtaining, with a first circuitry of an Ethernet network interface controller (NIC) for a first computing device that includes a central processing unit (CPU) interface to communicatively couple with a CPU and an Ethernet network interface to communicatively couple to a network
of compute devices, a request from a requestor device to access a memory at a data storage device, wherein the data storage device does not include the Ethernet NIC;
(Claim 17) wherein to obtain the request to access the memory at data storage device comprises to obtain the request from the CPU;
determining, by the first circuitry, whether the data storage device is located on the first compute device or accessible through a second compute device from among the network of compute devices; enabling, by the first circuitry, a non-volatile memory express driver; and providing, to the requestor device, access to the data storage device via use of the non-volatile memory express driver.
Claim 38. The method of claim 35, further comprising:
causing, with the circuitry, the data storage device to be powered on at the storage server based on a request sent, by the circuitry to a second circuitry of a second Ethernet NIC located at the storage server to power on the data storage device.
Claim 27. The method of claim 24, determining that the data storage device is accessible through the second compute device, wherein the method further comprises:
causing, by the first circuitry, the data storage device to be powered on at the second compute device by sending a request to a second circuitry of a second Ethernet NIC
located at the second compute device to power on the data storage device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-24, 26, 28-31, 33-37 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Conner et al. (US 2014/0122634 A1 – cited in the IDS) in view of Kagan et al. (US 9,696,942 B2).
As to claim 21, Conner teaches an apparatus (an apparatus in claim 1) comprising:
an Ethernet network interface controller (NIC) located on a host compute device (NIC at a first node A; paragraph [0033] and Ethernet link; paragraph [0034]), the Ethernet NIC to include a first interface to communicatively couple with a host central processing unit (CPU) (“Each NIC further includes … a processor interconnect interface 412”; paragraph [0036]) and a second interface to communicatively couple with a network of storage servers (“in FIG. 2, each of NICs A and Bare connected via respective Ethernet links 230 to a network 232”; paragraph [0028] and “This includes modifications to NICs 308a and 308b (NIC A and NIC B) to make them NUMA aware, as well as new components comprising a NIC-to-NIC interconnect 302 coupling NICs 308a and 308b in communication, along with a node filter table 304.”; paragraph [0033]), wherein the Ethernet NIC also includes circuitry (“Each NIC further includes packet processing logic 408, a DMA engine 410”; paragraph [0036]) to:
obtain a request to access a data storage device (“processors (and processor cores) are enabled to access different memory resources distributed across the platform”; paragraph [0024] and “The packet is received at NIC 308a from network 232 via Ethernet link 230a and is buffered in an input buffer on the NIC during a first operation”; paragraph [0034]); and
based on whether the data storage device is located on the host compute device or accessible through a storage server from among the network of storage servers (“During a second operation corresponding to an initial packet processing operation performed by NIC 308a, the packet header and/or packet payload for packet 228 is inspected, and applicable filter match input data is generated based on packet header field data and/or packet payload data, which is then employed by packet processing logic on NIC 308a as an input lookup against filters and/or rules defined in node filter table 304 ...” NIC 308a is local to node A. “ ... [T]he filters and/or rules in node filter table 304 enables the node of the memory resource to which applicable packet data is to be written to be identified. In this example, the memory resource node is node B, which has a corresponding NIC 308b.” NIC 308b is remote from node A; paragraph [0034]), provide access to the data storage device (“Accordingly, during a third operation, data corresponding to a copy of packet 228 is forwarded from the input buffer (or another buffer) on NIC 308a to an input buffer on NIC 308b. The copy of packet 228 is then processed during a fourth operation as if it was received by NIC 308b from network 232 via Ethernet 230b, resulting in a copy of packet 228 being written using a DMA write operation to either system memory 206b (operation 4a) or LL Cache 215b (operation 4b)”; paragraph [0034]).
Conner does not teach the request from the host CPU, and provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver.
However, Kagan teaches the Ethernet NIC receives request from the host CPU to access storage device (“Network operations by applications and other processes running on host computer are handled by a NIC driver program, which receives work requests from such processes”; col. 6, lines 33-36), and provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver (NIC driver program …places corresponding work queue elements (WQEs) in send and receive queues; col. 6, lines 33-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Kagan to the system of Conner because Kagan teaches a method that enabling applications to access remote storage devices over a network using a protocol, such as NVMe, that is defined for accessing local storage devices via the peripheral component interface bus (col. 5, lines 16-20), in which, the NVMe protocol provides a simple, fast and convenient means for application programs running on a host computer to access the storage devices (col. 5, lines 3-7).
As to claim 22, Conner as modified by Kagan teaches the apparatus of claim 21, the data storage device is located on the storage server, wherein to provide access to the host CPU to the data storage device via use of the non-volatile memory express driver is to include presenting the data storage device as being local to the host compute device (see Kagan: “enabling applications to access remote storage devices over a network using a protocol, such as NVMe, that is defined for accessing local storage devices via the peripheral component interface bus … most of the control functions are offloaded to the NICs”; col. 5, lines 16-38 and “the NVMe protocol provides a simple, fast and convenient means for application programs running on a host computer to access the storage devices”; col. 5, lines 3-7).
As to claim 23, Conner as modified by Kagan teaches the apparatus of claim 21, wherein a data storage device map indicative of locations of a plurality of data storage devices is used to determine whether the data storage device is located on the host compute device or located on the storage server (see Conner: the packet header and/or packet payload for packet is inspected … node filter table 34 … The filters and/or rules in node filter table 304 enables the node of the memory resource to which applicable packet data is to be written to be identified; paragraph [0034]).
As to claim 24, Conner as modified by Kagan teaches the apparatus of claim 23, wherein the circuitry is to receive the data storage device map from an orchestrator server communicatively coupled to the circuitry (see Conner: “Similarly, node B system memory 206b includes memory address space allocated to a NIC B device driver, a software application C, and a node filter table 304b.”, “The reverse process is performed for the request received at node B”; paragraph [0037] and “processors (and processor cores) are enabled to access different memory resources distributed across the platform.; paragraph [0024]; and “The packet is received at NIC 308a from network 232 via Ethernet link 230a and is buffered in an input buffer on the NIC during a first operation”; paragraph [0034]).
As to claim 26, Conner as modified by Kagan teaches the apparatus of claim 21, wherein the host CPU is to execute a workload on the host compute device (see Kagan: applications and other processes running on host computer are handled by a NIC driver program, which receives work requests from such processes”; col. 6, lines 33-36).
As to claim 28, Conner teaches one or more machine-readable storage media comprising a plurality of instructions stored thereon that (a machine-readable medium), in response to being executed (paragraph [0070]), cause circuitry of an Ethernet network interface controller (NIC) (“Each NIC further includes packet processing logic 408, a DMA engine 410”; paragraph [0036]) located on a host compute device to (NIC at a first node A; paragraph [0033] and Ethernet link; paragraph [0034]):
obtain, via a first interface coupled with a host central processing unit (CPU) (“Each NIC further includes … a processor interconnect interface 412”; paragraph [0036]), a request to access a data storage device (“processors (and processor cores) are enabled to access different memory resources distributed across the platform”; paragraph [0024] and “The packet is received at NIC 308a from network 232 via Ethernet link 230a and is buffered in an input buffer on the NIC during a first operation”; paragraph [0034]); and
based on whether the data storage device is located on the host compute device or accessible through a storage server (“During a second operation corresponding to an initial packet processing operation performed by NIC 308a, the packet header and/or packet payload for packet 228 is inspected, and applicable filter match input data is generated based on packet header field data and/or packet payload data, which is then employed by packet processing logic on NIC 308a as an input lookup against filters and/or rules defined in node filter table 304 ...” NIC 308a is local to node A. “ ... [T]he filters and/or rules in node filter table 304 enables the node of the memory resource to which applicable packet data is to be written to be identified. In this example, the memory resource node is node B, which has a corresponding NIC 308b.” NIC 308b is remote from node A; paragraph [0034]) from among a network of storage servers coupled to the circuitry via a second interface (“in FIG. 2, each of NICs A and B are connected via respective Ethernet links 230 to a network 232”; paragraph [0028] and “This includes modifications to NICs 308a and 308b (NIC A and NIC B) to make them NUMA aware, as well as new components comprising a NIC-to-NIC interconnect 302 coupling NICs 308a and 308b in communication, along with a node filter table 304.”; paragraph [0033]), provide access to the data storage device (“Accordingly, during a third operation, data corresponding to a copy of packet 228 is forwarded from the input buffer (or another buffer) on NIC 308a to an input buffer on NIC 308b. The copy of packet 228 is then processed during a fourth operation as if it was received by NIC 308b from network 232 via Ethernet 230b, resulting in a copy of packet 228 being written using a DMA write operation to either system memory 206b (operation 4a) or LL Cache 215b (operation 4b)”; paragraph [0034]).
Conner does not teach the request from the host CPU, and provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver.
However, Kagan teaches the Ethernet NIC receives request from the host CPU to access storage device (“Network operations by applications and other processes running on host computer are handled by a NIC driver program, which receives work requests from such processes”; col. 6, lines 33-36), and provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver (NIC driver program …places corresponding work queue elements (WQEs) in send and receive queues; col. 6, lines 33-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Kagan to the system of Conner because Kagan teaches a method that enabling applications to access remote storage devices over a network using a protocol, such as NVMe, that is defined for accessing local storage devices via the peripheral component interface bus (col. 5, lines 16-20), in which, the NVMe protocol provides a simple, fast and convenient means for application programs running on a host computer to access the storage devices (col. 5, lines 3-7).
As to claim 29, see rejection of claim 22 above.
As to claim 30, see rejection of claim 23 above.
As to claim 31, see rejection of claim 24 above.
As to claim 33, Conner as modified by Kagan teaches the one or more machine-readable storage media of claim 28, wherein the host CPU is to execute a workload on the host compute device.
As to claim 34, Conner teaches a method for accessing a data storage device (a method of claim 1), the method comprising:
obtaining, with circuitry of an Ethernet network interface controller (NIC) (“Each NIC further includes packet processing logic 408, a DMA engine 410”; paragraph [0036]) for a host computing device (NIC at a first node A; paragraph [0033] and Ethernet link; paragraph [0034]) that includes a first interface to communicatively couple with a host central processing unit (CPU) (“Each NIC further includes … a processor interconnect interface 412”; paragraph [0036]) and a second interface to communicatively couple to a network of storage servers (“in FIG. 2, each of NICs A and Bare connected via respective Ethernet links 230 to a network 232”; paragraph [0028] and “This includes modifications to NICs 308a and 308b (NIC A and NIC B) to make them NUMA aware, as well as new components comprising a NIC-to-NIC interconnect 302 coupling NICs 308a and 308b in communication, along with a node filter table 304.”; paragraph [0033]), a request to access a data storage device (“processors (and processor cores) are enabled to access different memory resources distributed across the platform”; paragraph [0024] and “The packet is received at NIC 308a from network 232 via Ethernet link 230a and is buffered in an input buffer on the NIC during a first operation”; paragraph [0034]); and
based on whether the data storage device is located on the host compute device or accessible through a storage server from among the network of storage servers (“During a second operation corresponding to an initial packet processing operation performed by NIC 308a, the packet header and/or packet payload for packet 228 is inspected, and applicable filter match input data is generated based on packet header field data and/or packet payload data, which is then employed by packet processing logic on NIC 308a as an input lookup against filters and/or rules defined in node filter table 304 ...” NIC 308a is local to node A. “ ... [T]he filters and/or rules in node filter table 304 enables the node of the memory resource to which applicable packet data is to be written to be identified. In this example, the memory resource node is node B, which has a corresponding NIC 308b.” NIC 308b is remote from node A; paragraph [0034]), provide access to the data storage device (“Accordingly, during a third operation, data corresponding to a copy of packet 228 is forwarded from the input buffer (or another buffer) on NIC 308a to an input buffer on NIC 308b. The copy of packet 228 is then processed during a fourth operation as if it was received by NIC 308b from network 232 via Ethernet 230b, resulting in a copy of packet 228 being written using a DMA write operation to either system memory 206b (operation 4a) or LL Cache 215b (operation 4b)”; paragraph [0034]).
Conner does not teach the request from the host CPU, and provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver.
However, Kagan teaches the Ethernet NIC receives request from the host CPU to access storage device (“Network operations by applications and other processes running on host computer are handled by a NIC driver program, which receives work requests from such processes”; col. 6, lines 33-36), and provide, to the host CPU, access to the data storage device via use of a non-volatile memory express driver (NIC driver program …places corresponding work queue elements (WQEs) in send and receive queues; col. 6, lines 33-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Kagan to the system of Conner because Kagan teaches a method that enabling applications to access remote storage devices over a network using a protocol, such as NVMe, that is defined for accessing local storage devices via the peripheral component interface bus (col. 5, lines 16-20), in which, the NVMe protocol provides a simple, fast and convenient means for application programs running on a host computer to access the storage devices (col. 5, lines 3-7).
As to claim 35, see rejection of claim 22 above.
As to claim 36, see rejection of claim 23 above.
As to claim 37, see rejection of claim 24 above.
As to claim 39, see rejection of claim 26 above.
Claims 25, 32 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Conner et al. (US 2014/0122634 A1 – cited in the IDS) in view of Kagan et al. (US 9,696,942 B2) further in view of Daud et al. (US 9,276,900 B1 – cited in the IDS).
As to claim 25, Conner as modified by Kagan does not teach the data storage device is located on the storage server, wherein the circuitry is further to: cause the data storage device to be powered on at the storage server based on a request sent to a second circuitry of a second Ethernet NIC located at the storage server to power on the data storage device.
However, in the same field of endeavor, Daud teaches cause the data storage device to be powered on at the storage server based on a request sent to a second circuitry of a second Ethernet NIC located at the storage server to power on the data storage device (“local reads and writes are coordinated with the other controllers. Controllers are programmed to power up on read and writes.” and “Similarly, controller 456 may communicate with other controllers to coordinate reads and/or writes of data among a plurality of storage devices. In at least one of various embodiments, controller 456 may be enabled to control power provided to storage device 452 such that storage device 452 can be powered down when removed or not in a shingle, powered up when added to a shingle, powered up to fulfill a read request and power down after completion of the read request, or the like.”; col. 15, lines 12-20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Conner as modified by Kagan to substitute powering up from Daud for the power supply from Conner as modified by Kagan to improve system effectiveness. The motivation would have been to lower resource power cost not providing power to all the storage resources when they have not been accessed.
As to claims 32 and 38, see rejection of claim 25 above.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Conner et al. (US 2014/0122634 A1 – cited in the IDS) in view of Kagan et al. (US 9,696,942 B2) further in view of Gorodetsky et al. (US 2006/0067318 Al – cited in the IDS).
As to claim 27, Conner as modified by Kagan does not teach the circuitry comprises a field-programmable gate array (FPGA).
However, in the same field of endeavor, Gorodetsky teaches the first circuitry comprises a field-programmable gate array (FPGA) ("Network interfaces 26A and 26B may comprise embedded controllers, data processors, hardware logic circuits, configured field-programmable gate arrays (FPGAS), and/or other suitable local control mechanisms which facilitate operation as described herein."; paragraph [0106]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Gorodetsky to the system of Conner as modified by Kagan by substitute FPGA from Gorodetsky for the controller circuitry from Conner as an equivalent substitution. The motivation would have been to provide improved efficiency for processing routing instructions and by leveraging processing efficiency provided by FPGA modules.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bradley (US 6,948,001 B1) teaches an independent storage node is disclosed that includes a processor and transport hardware in communication with the processor that is capable of communicating data via a transport connection. Executing on the processor is modular storage software that comprises a plurality of software modules and a module interface. The module interface allows dynamic binding of the software modules and is capable of executing on a plurality of processor types by using particular software modules related to a specific processor type.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIEM K CAO whose telephone number is (571)272-3760. The examiner can normally be reached Monday-Friday 8:00am-4:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DIEM K CAO/Primary Examiner, Art Unit 2196
DC
December 10, 2025