DETAILED ACTION
This Office Actions is in response to communication filed on 07/10/2023. Claims 1 – 17 are pending. Claim 1, 9, and 17 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 9, and 17 objected to because of the following informalities: “wherein the performance metrics indicate host I/O request processing latency”. The first uses of the acronym “I/O” must fully spell out as “Input/Output”, based on paragraph [0004] from the Specification, such as: “wherein the performance metrics indicate host Input/Output (I/O) request processing latency”. After that, the uses of the acronym “I/O” does not need to fully spell out.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 – 8, 9, 13 – 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over KANG et al. US Pub. No. US 20180046512 A1 (hereafter KANG), in further view of Koren et al. US Pub. No. US 20240012679 A1 (hereafter Koren) and Waters et al. US Pub. No. US 20140052882 A1 (hereafter Waters).
Regarding claim 1, KANG teaches the invention substantially as claimed: A method comprising: continuously monitoring performance metrics for each processor core (e.g. FIG. 7 and [0052]: “FIG. 7 shows a flowchart of an example dynamic mapper of a data processing system, according to one embodiment. The dynamic mapper is initialized (701) by validating configuration and verifying accesses to sub components (e.g., a system status monitor) that need to be monitored, and preparing data structure to collect information (e.g., performance parameters), and starting a monitoring thread to start collecting the information. After being initialized, the dynamic mapper starts to collect various performance parameters from a system status monitor (702). Examples of the performance parameters include, but are not limited to, a data processing rate (DPR) and an I/O processing rate (IOR) of CPU cores of the data processing system.”) The citation discloses the monitoring and collecting information that comprise performance parameters/performance metrics of CPU cores.
......... and wherein the performance metrics indicate host I/O request processing latency and an amount of processing capacity of each processor core (e.g. [0052]: “Examples of the performance parameters include, but are not limited to, a data processing rate (DPR) and an I/O processing rate (IOR) of CPU cores of the data processing system.”) the citation discloses the performance metric comprises the data processing rate/processing capacity, and the I/O processing rate/ I/O request processing latency, of CPU cores of the system.
and assigning host I/O request processing and background work item processing performed by the storage system application to individual processor cores based on the performance metrics, (e.g. FIG. 7 and [0052]: “Examples of the performance parameters include, but are not limited to, a data processing rate (DPR) and an I/O processing rate (IOR) of CPU cores of the data processing system. The dynamic mapper tries to saturate CPU cores by keeping the IOR as close to the DPR as possible. When the IOR is greater than or equal to the DPR (703), the dynamic mapper computes the number of CPU cores allocated for I/O tasks and compute tasks (705). When the DPR is greater than or equal to the IOR (703), the dynamic mapper checks whether devices (e.g., storage devices 610 of FIG. 6) are saturated (704). A device is saturated when its I/O bandwidth or IOPSs is fully utilized, therefore sending more I/O commands to a saturated device would not give any performance benefit. If the devices are not saturated (704), the dynamic mapper also computes the number of CPU cores allocated for I/O tasks and compute tasks (705). The dynamic mapper adjusts the number of I/O and compute threads and/or affinity of the I/O and compute threads to the CPU groups based on the number of CPU cores allocated for the I/O tasks and the compute tasks (706).”) The citation discloses the concept of using the performance parameters (comprise DPR and IOR), to compute the number of CPU cores allocated for I/O tasks and compute tasks
KANG fails to teach ....... processor core in a shared portion of processor cores in a data storage system, wherein each processor core in the shared portion of the processor cores is shared between a storage system application located in the data storage system and a containerized service also located in the data storage system; such that the host I/O request processing is preferentially assigned to processor cores that have relatively lower host I/O request processing latency than other processor cores, and the background work item processing is preferentially assigned to processor cores that have higher amounts of processing capacity available for use by the storage system application than other processor cores;
However, Koren teaches processor core in a shared portion of processor cores in a data storage system, wherein each processor core in the shared portion of the processor cores is shared between a storage system application located in the data storage system and a containerized service also located in the data storage system, (e.g. FIG. 1 and [0003]: “In the disclosed technology, a shared portion of the processor cores in a data storage system are allocated for sharing between a storage system application and a containerized service that also executes in the data storage system.”)
......... of each processor core in the shared portion of the processor cores that is available for use by the storage system application; (e.g. [0004]: “The storage system application preferentially uses processor cores in the shared portion of the processor cores to execute background tasks that are performed by the storage system application.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the processor core in a shared portion of processor cores in a data storage system, wherein each processor core in the shared portion of the processor cores is shared between a storage system application located in the data storage system and a containerized service also located in the data storage system, ......... of each processor core in the shared portion of the processor cores that is available for use by the storage system application, as taught in Koren’s invention into KANG’s invention because the addition features would help the system to improve processor utilization, reduce resource contention between workloads, and maintain overall system performance even when the workload changes dynamically.
However, Waters teaches such that the request processing is preferentially assigned to processor cores that have relatively lower request processing latency than other processor cores, (e.g. [0046]: “Upon identifying characterization(s) associated with the one or more tasks, some embodiments further determine information and/or characterizations associated with one or more processor cores, such as through analyzing core data structure(s) 310........ Thus, it should be noted that a variety of information can be obtained: information characterizing processor core(s), information characterizing task(s) running on a processor core, as well as information characterizing task(s) ready to be assigned to a processor when core. Based on this information, one or more task(s) can be (re)assigned to a processor core. For example, latency-sensitive SWInt and latency-sensitive thread of tasks 312 may have originally been assigned to processor core 0 or 1, but are reassigned to an idle processor core due to either the latency-sensitive nature of the task(s) and/or the busy state of the originally assigned processor core(s).” and FIG. 5) The citation discloses the concept of determining the character associated with processor cores that suitable for processing latency-sensitive tasks, and uses that information to assign or reassign the tasks to the corresponding cores for better performing of the tasks/lower processing latency.The teaching of Waters does not clearly indicate the requests/tasks is host I/O request. The host I/O request is taught by KANG.
and the processing is preferentially assigned to processor cores that have higher amounts of processing capacity available for use by the system than other processor cores; (e.g. [0046]: “Upon identifying characterization(s) associated with the one or more tasks, some embodiments further determine information and/or characterizations associated with one or more processor cores, such as through analyzing core data structure(s) 310........ Thus, it should be noted that a variety of information can be obtained: information characterizing processor core(s), information characterizing task(s) running on a processor core, as well as information characterizing task(s) ready to be assigned to a processor when core. Based on this information, one or more task(s) can be (re)assigned to a processor core....... The non-latency sensitive SWInt and/or thread can either be (re)assigned to an idle processor core, or be assigned to a busy processor core in order to keep idle processor core(s) readily available for latency sensitive tasks. Thus, tasks can be (re)assigned to processing core(s) based upon characteristics of not only the tasks, but characteristics of the processing core(s), and what the processing core(s) might be currently running as well (e.g. interrupt, task, etc.).” and FIG. 5 and FIG. 6) The citation discloses the concept of gathering the processor core usage information/amounts of processing capacity available, and uses that information to assign the tasks on the optimal processor core. The teaching of Waters does not clearly indicate the process is background work item. The background work item is taught by Koren.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the such that the request processing is preferentially assigned to processor cores that have relatively lower request processing latency than other processor cores, and the processing is preferentially assigned to processor cores that have higher amounts of processing capacity available for use by the storage system application than other processor cores, as taught in Waters’s invention into KANG’s invention because the addition features would help the system to reduce delay, better workload balancing, more efficient use of shared processor resources, and better overall system performance.
Regarding claim 5, KANG, in view of Koren and Waters, discloses the method of claim 1, and Koren further teaches wherein the data storage system further includes a non-shared portion of processor cores; (e.g. [0023]: “In the disclosed technology, a shared portion of the processor cores in the data storage system are allocated for sharing between the storage system application and the containerized service, and a non-shared portion of the processor cores are allocated for exclusive use by the storage system application.”)
wherein each processor core in the non-shared portion of processor cores in the data storage system executes only one of the set consisting of i) host I/O request processing performed by the storage system application, (e.g. [0030]: “In some embodiments, the storage system application may preferentially use processor cores in the non-shared portion of the processor cores to execute host I/O request processing by, in response to a determination that the total number of processor cores currently needed to execute the background tasks is greater than the total number of processor cores within the shared portion of the processor cores, using only all of those processor cores within the non-shared portion of the processor cores that are not currently being used to execute background tasks to execute host I/O request processing.”)
and ii) background work item processing performed by the storage system application;
and wherein each processor core in the shared portion of processor cores in the data storage system executes, in addition to the containerized service, only one of the set consisting of i) host I/O request processing performed by the storage system application, (e.g. [0023]: “In the disclosed technology, a shared portion of the processor cores in the data storage system are allocated for sharing between the storage system application and the containerized service” and [0029]: “In response to a determination that multiple processor cores within the shared portion of the processor cores are currently being used to execute host I/O request processing, the storage system application may select specific amounts of host I/O request processing to be assigned to individual ones of the processor cores within the shared portion of the processor cores currently being used to execute host I/O request processing application, based on loading feedback obtained for individual ones of the processor cores in the shared portion of the processor cores currently being used to execute host I/O request processing.”)
and ii) background work item processing performed by the storage system application.
Regarding claim 6, KANG, in view of Koren and Waters, discloses the method of claim 6, and Koren further teaches wherein at least one of the processor cores in the non-shared portion of the processor cores in the data storage system executes host I/O request processing; (e.g. [0050]: “Dynamic Core Assignment Logic 142 preferentially uses processor cores in Non-Shared Processor Cores 134 to execute Host I/O Request Processing Logic 138.”)
and wherein at least one of the processor cores in the non-shared portion of the processor cores in the data storage system executes background work items. (e.g. [0006]: “at least one of the processor cores within the non-shared portion of the processor cores to execute the background tasks performed by the storage system application.”)
Regarding claim 7, KANG, in view of Koren and Waters, discloses the method of claim 1, and Koren further teaches wherein the containerized service provides a file-based data storage service; and wherein the storage system application provides a block-based data storage service. (e.g. [0004]: “For example, the containerized service may provide a file-based data storage service to one or more hosts, and the storage system application may provide a block-based data storage service to one or more hosts.”)
Regarding claim 8, KANG, in view of Koren and Waters, discloses the method of claim 7, and Koren further teaches wherein the host I/O request processing performed by the storage system application comprises processing of host I/O requests received by the data storage system from at least one host computing device; (e.g. FIG. 1, and [0039] – [0040])
and wherein the background work item processing performed by the storage system application includes flushing host data stored in a cache of the data storage system to at least one non-volatile data storage drive of the data storage system. (e.g. [0041]: “One example of background processing of host data that is performed by Background Task Logic 140 is flushing of host data indicated by I/O write requests from Cache 146 to Physical Non-Volatile Data Storage Drives 126”)
Regarding claim 9, it is a data storage system claim having similar limitations cited in claim 1, so it is also rejected under the same rational.
Regarding claims 13 – 16, they are data storage system claim having similar limitations cited in claims 5 – 8, so they are also rejected under the same rational.
Regarding claim 17, it is a computer program product including a non-transitory computer readable medium claim having similar limitations cited in claim 1, so it is also rejected under the same rational.
Claims 2, 4, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over KANG, Koren and Waters, in further view of Kamran et al. US Pub. No. US 20210349762 A1 (hereafter Kamran).
Regarding claim 2, KANG, in view of Koren and Waters, discloses the method of claim 1, but fails to teach wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core average host I/O (Input/Output) request processing latency; and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes preferentially assigning host I/O request processing to processor cores in the shared portion of the processor cores that have lower average host I/O request processing latency than other processor cores in the shared portion of the processor cores.
However, Kamran teaches wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core average host I/O (Input/Output) request processing latency; (e.g. [0003]: “An average input/output (IO) latency for an operating system thread executing on the CPU core of the plurality of CPU cores may be determined.”)
and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes preferentially assigning host I/O request processing to processor cores in the shared portion of the processor cores that have lower average host I/O request processing latency than other processor cores in the shared portion of the processor cores. (e.g. [0004]: “Adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores may include determining whether an average block application utilization of the plurality of CPU cores is less than a first predefined block application utilization threshold. Adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores may include decreasing the operating system thread IO polling cadence for the at least one operating system thread executing on the at least one CPU core in response to determining that the average IO latency for the operating system thread executing on the CPU core is greater than the average IO latencies of the other CPU cores of the plurality of CPU cores by more than a predefined IO latency threshold and that the average block application utilization of the plurality of CPU cores is less than the predefined block application utilization threshold.”) The citation discloses the concept of monitoring per core average I/O latency for OS threads on each CPU core and compares these average I/O latency with other cores, and use the results to determine higher or lower latency cores and adjust the I/O handling behavior accordingly. By combining this concept with the teaching of previous cited references in the rejection of claim 1 about assigning the processing to the appropriate core, one with ordinary skill in the art would be able to come up with the claim invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the cause the wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core average host I/O (Input/Output) request processing latency; and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes preferentially assigning host I/O request processing to processor cores in the shared portion of the processor cores that have lower average host I/O request processing latency than other processor cores in the shared portion of the processor cores, as taught in Kamran’s invention into KANG, Koren and Waters’s invention because the newly added limitation would enable the system to provide better view of how efficiently each cores handle request over time and can route request to the most suitable core, which helps to reduce overall completion times, improve throughput, and maintains stable performance processing environment.
Regarding claim 4, KANG, in view of Koren and Waters, discloses the method of claim 1, but fails to teach wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core total utilization; and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes assigning processing of at least one host I/O request to one or more processor cores in the shared portion of the processor cores in response to detecting that those processor cores have a total utilization that is less than a predetermined low utilization threshold.
However, Kamran teaches wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core total utilization; and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes assigning processing of at least one host I/O request to one or more processor cores in the shared portion of the processor cores in response to detecting that those processor cores have a total utilization that is less than a predetermined low utilization threshold. (e.g. [0004]: “Adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores may include determining whether an average block application utilization of the plurality of CPU cores is less than a first predefined block application utilization threshold. Adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores may include decreasing the operating system thread IO polling cadence for the at least one operating system thread executing on the at least one CPU core in response to determining that the average IO latency for the operating system thread executing on the CPU core is greater than the average IO latencies of the other CPU cores of the plurality of CPU cores by more than a predefined IO latency threshold and that the average block application utilization of the plurality of CPU cores is less than the predefined block application utilization threshold.”).The citation discloses the concept of monitoring per CPU core utilization, and using the metrics to compare with the utilization threshold. This concept is similar to the claim invention because both reply on per-core utilization information to guide the allocation of processing activity across multiple cores. By combining this concept with the teaching of previous cited references in the rejection of claim 1 about assigning the processing to the appropriate core, one with ordinary skill in the art would be able to come up with the claim invention.
Regarding claim 10, it is a data storage system claim having similar limitations cited in claim 2, so it is also rejected under the same rational.
Regarding claim 12, it is a data storage system claim having similar limitations cited in claim 4, so it is also rejected under the same rational.
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over KANG, Koren and Waters, in further view of Ajmera et al. US Pub. No. US 20220012108 A1 (hereafter Ajmera).
Regarding claim 3, KANG, in view of Koren and Waters, discloses the method of claim 1, but fails to teach wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core percentage of total processing capacity consumed by execution of the containerized service; and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes preferentially assigning background work item processing to processor cores in the shared portion of the processor cores that have a lower percentage of their total processing capacity consumed by execution of the containerized service than other processor cores in the shared portion of the processor cores.
However, Ajmera teaches wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core percentage of total processing capacity consumed by execution of the containerized service; (e.g. [0034]: “In one embodiment, each processing core 125 is associated with a high threshold and a low threshold. In one embodiment, the high threshold and the low threshold associated with a processing core 125 can be configured as a percentage of that processing core's processing capacity. For example, the high threshold can be configured to be 80 percent of the processing core's processing capacity and the low threshold can be configured to be 30 percent of the processing core's processing capacity.”) The citation discloses the percentage of total processing capacity of a processing core, which is similar the claim because both involve tracking performance metrics on a per-core using percentage of total capacity.
and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes preferentially assigning background work item processing to processor cores in the shared portion of the processor cores that have a lower percentage of their total processing capacity consumed by execution of the containerized service than other processor cores in the shared portion of the processor cores; (e.g. FIG. 4 and [0047]: “At decision block 430, the network device determines whether the value is higher than a high threshold associated with the current processing core or lower than a low threshold associated with the current processing core. If not, at block 450, the network device keeps the polling thread on the current processing core and the process returns to block 420. In one embodiment, the network device configures the thresholds (e.g., the high threshold and/or the low threshold) associated with the first processing core (e.g., based on the hardware capabilities and application needs). For example, the network device may configure the low threshold associated with the first processing core and/or the high threshold associated with the first processing core to be a percentage of a processing capacity of the first processing core (e.g., configure the low threshold to be 30 percent of the first processing core's processing capacity and configure the high threshold to be 80 percent of the first processing core's processing capacity).”) The citation discloses the concept of using high and low thresholds as percentages of the core’s total processing capacity (30% vs 80%), which is similar to the limitation because both user per-core percentage of processing capacity to make the processing decision. By combining this concept with the teaching of previous cited references in the rejection of claim 1 about assigning the processing to the appropriate core, one with ordinary skill in the art would be able to come up with the claim invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the cause the wherein the performance metrics monitored for each processor core in the shared portion of the processor cores include a per-core percentage of total processing capacity consumed by execution of the containerized service; and wherein the assigning of host I/O request processing and background work item processing performed by the storage system application includes preferentially assigning background work item processing to processor cores in the shared portion of the processor cores that have a lower percentage of their total processing capacity consumed by execution of the containerized service than other processor cores in the shared portion of the processor cores, as taught in Ajmera’s invention into KANG, Koren and Waters’s invention because the newly added limitation would enable the system to better understand the current workload on each core, so the system can avoid assigning workload to cores that already heavily loaded, which improve overall efficiency and stability of the system, and maintain smoother and more predictable overall performance.
Regarding claim 11, it is a data storage system claim having similar limitations cited in claim 3, so it is also rejected under the same rational.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20210124615 A1: a method includes receiving, in a monitor, performance metric information from performance monitors of a processor including at least a first core type and a second core type, and storing, by the monitor, an application identifier associated with an application in execution and the performance metric information for the first core type and the second core type, in a table; obtaining the performance metric information for the first core type and the second core type, and scheduling, by the scheduler, one or more threads of a first application associated with the first application identifier to one or more of the plurality of cores based at least in part on the performance metric information of the at least one entry.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs
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/TUAN M NGUYEN/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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