Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the RCE filed on 12/29/2025.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-16, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Chinese Patent Application Publication CN 110912402 A, hereafter referred to as “Lin”) in view of Fu et al. (Chinese Patent Application Publication CN 110994995 A, hereafter referred to as “Fu”) and further in view of Ravi et al. (US Patent Application Publication US 2021/0067182 A1, hereafter referred to as “Ravi”) Regarding claim 1, Lin discloses (see Fig. 7, Fig. 2, Fig. 3A, and Fig. 3B) a converter (see buck-boost converter of Fig. 2) comprising: a first circuit configured to perform a buck operation (comprising SWA, SWB, C1, DA, DB, CL1); a second circuit configured to perform a boost operation (comprising SWC, SWD, C2, DC, DD, CL2); an inductor (L) coupling the first circuit and the second circuit; and a third circuit (comprising SW and R) comprising a first resistor (R) and a first switch (SW), wherein the first circuit comprises a first field effect transistor (FET) (SWA), a second FET (SWB), a first capacitor (C1), and a first drive circuit (comprising DA, DB), wherein the first capacitor is coupled to the first FET and the second FET (C1 is coupled to SWA and SWB at node LX1), wherein the first drive circuit is coupled to the first FET, the second FET, and the first capacitor (DA is coupled to SWA and SWB and C1 at node LX1), wherein the second circuit comprises a third FET (SWD), a fourth FET (SWC), a second capacitor (C2), a second drive circuit (comprising DD, DC), and a first Zener diode (CL2, see [0081] “the first clamping unit CL1 and second clamping unit CL2 may be a Zener diode (Zener diode)”), wherein the second capacitor is coupled to the third FET and the fourth FET (C2 is coupled to SWD and SWC at node LX2), wherein the second drive circuit is coupled to the third FET, the fourth FET, the second capacitor, and the first Zener diode (DD is coupled to SWD, SWC, C2, and CL2 at node LX2), wherein the first switch is configured to conduct current in direction from a first node (node of BST1) coupled to the first drive circuit and the first capacitor (node of BST1 is coupled to DA and C1) to a second node (node of BST2) coupled to the second drive circuit, the second capacitor and the first Zener diode (node of BST2 is coupled to DD and C2 and CL2), and wherein (see Fig. 3A) the second capacitor is charged based on current (ICH) introduced from the first node through the first resistor and the first switch to maintain a voltage (VBST2) of the second drive circuit (see [0066] “the control unit CU controls the fifth switch SW on, causing the first boost node BST1 and the second boost node BST2 to form a channel, and the first boost node BST1 to the second boost node BST2 charging (e.g., charging current ICH), by keeping the second boost node BST2 potential (i.e. the second boost capacitor voltage) VBST2, such as maintaining the output voltage VOUT plus the working voltage VDD. to ensure that the fourth switch SWD can maintain conduction.”, Examiner’s Note: Fig. 3A and Fig. 3B disclose the equivalent operation modes of the buck-boost converter of Fig. 7). Lin does not disclose wherein the converter is part of a wireless communication system. However, Ravi teaches (see Fig. 14, Fig. 15, Fig. 16A) the converter (see DCDC converter “VRF” of Fig. 16A) is part of a wireless communication system (see wireless communication system of Fig. 14, where Fig. 16A is a detailed description of each of “Transceiver Chains” of Fig. 14). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the converter is part of a wireless communication system, as taught by Ravi, because it can help provide a wide range of voltages for wireless communication systems. Lin does not disclose wherein the first switch comprises a first diode, wherein the first diode is configured to reduce or prevent current flowing from the second node to the first node. However, Fu teaches (see Fig. 3) wherein the first switch (comprising D1, Q7) comprises a first diode (D1), wherein the first diode (D1) is configured to reduce or prevent current flowing from the second node to the first node (D1 is configured to prevent current flowing from the node of BST2 to the node of BST1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the first switch comprises a first diode and wherein the first diode is configured to reduce or prevent current flowing from the second node to the first node, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor.
Regarding claim 2, Lin discloses (see Fig. 7) wherein the first drive circuit is coupled to a first gate of the first FET (GA) and a second gate of the second FET (GB) (DA is coupled to GA and DB is coupled to GB), and wherein the second drive circuit is coupled to a third gate of the third FET (GD) and a fourth gate of the fourth FET (GC) (DD is coupled to GD and DC is coupled to GC).
Regarding claim 3, Lin discloses (see Fig. 7) wherein the first capacitor is coupled to the first FET and the second FET at a third node (node LX1) to which a source of the first FET and a drain of the second FET are coupled (the source of SWA and the drain of SWB are coupled to C1 at node LX1), and wherein the second capacitor is coupled to the first Zener diode, the third FET, and the fourth FET at a fourth node (node LX2) to which a source of the third FET and a drain of the fourth FET are coupled (C2, CL2, the source of SWD and the drain of SWC are coupled at node LX2), and is coupled to the first switch through the first resistor (C2 is coupled to SW through R). Lin does not disclose wherein the first switch comprises a first diode. However, Fu teaches (see Fig. 3) wherein the first switch (Q7, D1) comprises a first diode (D1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the first switch comprises a first diode, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor.
Regarding claim 4, Lin discloses (see Fig. 7) wherein the inductor is disposed between the third node (node LX1) and the fourth node (node LX2) (L is disposed between node LX1 and node LX2).
Regarding claim 5, Lin discloses (see Fig. 7) wherein the first Zener diode is coupled to the second capacitor in parallel (CL2 is coupled to C2 in parallel).
Regarding claim 6, Lin discloses (see Fig. 7) wherein the converter further comprises a second Zener diode (CL1), wherein the first circuit comprises the second Zener diode (the first circuit comprising SWA, SWB, C1, DA, DB, CL1 comprises CL1), and wherein the second Zener diode is coupled to the first drive circuit (CL1 is coupled to DA). Lin does not disclose wherein the converter further comprises a second resistor, and a fourth circuit, the fourth circuit comprising a second diode, and wherein the fourth circuit couples the first node and the second node. However, Fu teaches (see Fig. 3) wherein the converter further comprises a second resistor (R7), a fourth circuit (comprising D2, Q8), the fourth circuit comprising a second diode (D2), and wherein the fourth circuit couples the first node (node of BST1) and the second node (node of BST2) (D2 and Q8 couple the node of BST1 and the node of BST2 via R7). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the converter further comprises a second resistor, and a fourth circuit, the fourth circuit comprising a second diode, and wherein the fourth circuit couples the first node and the second node, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor.
Regarding claim 7, Lin discloses (see Fig. 7) wherein the first capacitor is coupled to the first FET, the second FET, and the second Zener diode at a third node (node LX1) (C1 is coupled to SWA, SWB, and CL1 at node LX1) to which a source of the first FET and a drain of the second FET are coupled (the source of SWA and the drain of SWB is coupled to node LX1).
Regarding claim 8, Lin discloses (see Fig. 7) wherein the second Zener diode is coupled to the first capacitor in parallel (CL1 is coupled to C1 in parallel).
Regarding claim 9, Lin discloses (see Fig. 7) wherein a drain of the first FET is coupled to an input power (VIN) of the converter (the drain of SWA is coupled to VIN), and wherein a drain of the third FET is coupled to an output power (VOUT) (the drain of SWD is coupled to VOUT). Lin does not disclose wherein the output power comprises a power amplifier.
However, Ravi teaches (see 16A) wherein the output power (output of VFR) comprises a power amplifier (“amp”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the output power comprises a power amplifier, as taught by Ravi, because it can help provide a wide range of desired voltages for various power amplifiers in wireless communication systems.
Regarding claim 10, Lin discloses (see Fig. 7) wherein the converter further comprises a first bias structure (comprising VDD and D1) and a second bias structure (comprising VDD and D2), wherein the first bias structure comprises a first bias power (VDD) and a first bias diode (D1) and is coupled to the first node (coupled to node BST1), and wherein the second bias structure comprises a second bias power (VDD) and a second bias diode (D2) and is coupled to the second node (coupled to node BST2).
Regarding claim 11, Lin discloses (see Fig. 7) a converter (see buck-boost converter of Fig. 2) comprising: a first circuit configured to perform a buck operation (comprising SWA, SWB, C1, DA, DB, CL1); a second circuit configured to perform a boost operation (comprising SWC, SWD, C2, DC, DD, CL2); an inductor (L) coupling the first circuit and the second circuit; and a third circuit (comprising SW and R) comprising a first resistor (R) and a first switch (SW), wherein the first circuit comprises a first field effect transistor (FET) (SWA), a second FET (SWB), a first capacitor (C1), and a first drive circuit (comprising DA, DB), wherein the first capacitor is coupled to the first FET and the second FET (C1 is coupled to SWA and SWB at node LX1), wherein the first drive circuit is coupled to the first FET, the second FET, and the first capacitor (DA is coupled to SWA and SWB and C1 at node LX1), wherein the second circuit comprises a third FET (SWD), a fourth FET (SWC), a second capacitor (C2), a second drive circuit (comprising DD, DC), and a first Zener diode (CL2, see [0081] “the first clamping unit CL1 and second clamping unit CL2 may be a Zener diode (Zener diode)”), wherein the second capacitor is coupled to the third FET and the fourth FET (C2 is coupled to SWD and SWC at node LX2), wherein the second drive circuit is coupled to the third FET, the fourth FET, the second capacitor, and the first Zener diode (DD is coupled to SWD, SWC, C2, and CL2 at node LX2), wherein the first switch is configured to conduct current in direction from a first node (node of BST1) coupled to the first drive circuit and the first capacitor (node of BST1 is coupled to DA and C1) to a second node (node of BST2) coupled to the second drive circuit, the second capacitor and the first Zener diode (node of BST2 is coupled to DD and C2 and CL2), and wherein (see Fig. 3A) the second capacitor is charged based on current (ICH) introduced from the first node through the first resistor and the first switch to maintain a voltage (VBST2) of the second drive circuit (see [0066] “the control unit CU controls the fifth switch SW on, causing the first boost node BST1 and the second boost node BST2 to form a channel, and the first boost node BST1 to the second boost node BST2 charging (e.g., charging current ICH), by keeping the second boost node BST2 potential (i.e. the second boost capacitor voltage) VBST2, such as maintaining the output voltage VOUT plus the working voltage VDD. to ensure that the fourth switch SWD can maintain conduction.”, Examiner’s Note: Fig. 3A and Fig. 3B disclose the equivalent operation modes of the buck-boost converter of Fig. 7). Lin does not disclose a base station of a wireless communication system, the base station comprising: at least one processor; a plurality of radio frequency (RF) chains coupled to the at least one processor; a plurality of antenna elements coupled to the plurality of RF chains, wherein each RF chain of the plurality of RF chains comprises a converter and a power amplifier. However, Ravi teaches (see Fig. 14, Fig. 15, Fig. 16B) a base station of a wireless communication system (see Fig. 14 and [0149 ] “the device 1400 may be implemented as an access point or base station”), the base station comprising: at least one processor (1402); a plurality of radio frequency (RF) chains (1412.1, 1412.2, …, 1412.N) coupled to the at least one processor; a plurality of antenna elements (1414.1, 1414.2, …, 1414.N) coupled to the plurality of RF chains, wherein each RF chain of the plurality of RF chains comprises (see Fig. 16B) a converter (DC-DC Conv. 1, …, DC-DC Conv. N) and a power amplifier (“amp” of each slice). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin to be part of a base station of a wireless communication system, the base station comprising: at least one processor; a plurality of radio frequency (RF) chains coupled to the at least one processor; a plurality of antenna elements coupled to the plurality of RF chains, wherein each RF chain of the plurality of RF chains comprises a converter and a power amplifier, as taught by Ravi, because it can help provide a wide range of voltages for wireless communication systems. Lin does not disclose wherein the first switch comprises a first diode, wherein the first diode is configured to reduce or prevent current flowing from the second node to the first node. However, Fu teaches (see Fig. 3) wherein the first switch (comprising D1, Q7) comprises a first diode (D1), wherein the first diode (D1) is configured to reduce or prevent current flowing from the second node to the first node (D1 is configured to prevent current flowing from the node of BST2 to the node of BST1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the first switch comprises a first diode and wherein the first diode is configured to reduce or prevent current flowing from the second node to the first node, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor.
Regarding claim 12, Lin discloses (see Fig. 7) wherein the first drive circuit is coupled to a gate of the first FET (GA) and a gate of the second FET (GB) (DA is coupled to GA and DB is coupled to GB), and wherein the second drive circuit is coupled to a gate of the third FET (GD) and a gate of the fourth FET (GC) (DD is coupled to GD and DC is coupled to GC).
Regarding claim 13, Lin discloses (see Fig. 7) wherein the first capacitor is coupled to the first FET and the second FET at a third node (node LX1) to which a first source of the first FET and a second drain of the second FET are coupled (the source of SWA and the drain of SWB are coupled to C1 at node LX1), and wherein the second capacitor is coupled to the first Zener diode, the third FET, and the fourth FET at a fourth node (node LX2) to which a source of the third FET and a drain of the fourth FET are coupled (C2, CL2, the source of SWD and the drain of SWC are coupled at node LX2), and is coupled to the first switch through the first resistor (C2 is coupled to SW through R). Lin does not disclose wherein the first switch comprises a first diode. However, Fu teaches (see Fig. 3) wherein the first switch (Q7, D1) comprises a first diode (D1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the first switch comprises a first diode, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor.
Regarding claim 14, Lin discloses (see Fig. 7) wherein the inductor is disposed between the third node and the fourth node (L is disposed between node LX1 and node LX2).
Regarding claim 15, Lin discloses (see Fig. 7) wherein the first Zener diode is coupled to the second capacitor in parallel (CL2 is coupled to C2 in parallel).
Regarding claim 16, Lin discloses (see Fig. 7) wherein the converter further comprises a second Zener diode (CL1), wherein the first circuit comprises the second Zener diode (the first circuit comprising SWA, SWB, C1, DA, DB, CL1 comprises CL1), and wherein the second Zener diode is coupled to the first drive circuit (CL1 is coupled to DA). Lin does not disclose wherein the converter further comprises a second resistor, and a fourth circuit, the fourth circuit comprising a second diode, and wherein the fourth circuit couples the first node and the second node. However, Fu teaches (see Fig. 3) wherein the converter further comprises a second resistor (R7), a fourth circuit (comprising D2, Q8), the fourth circuit comprising a second diode (D2), and wherein the fourth circuit couples the first node (node of BST1) and the second node (node of BST2) (D2 and Q8 couple the node of BST1 and the node of BST2 via R7). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the converter further comprises a second resistor, and a fourth circuit, the fourth circuit comprising a second diode, and wherein the fourth circuit couples the first node and the second node, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor.
Regarding claim 21, Lin discloses (see Fig. 7) wherein the converter further comprises a first bias structure (comprising VDD and D1) and a second bias structure (comprising VDD and D2), wherein the first bias structure comprises a first bias power (VDD) and a first bias diode (D1) and is coupled to the first node (coupled to node BST1), and wherein the second bias structure comprises a second bias power (VDD) and a second bias diode (D2) and is coupled to the second node (coupled to node BST2).
Regarding claim 22, Lin discloses (see Fig. 7) wherein the first drive circuit is directly coupled to the first FET and the first capacitor, and coupled to the second FET through a first inverter, and wherein the second drive circuit is directly coupled to the third FET, the second capacitor, and the first Zener diode, and coupled to the fourth FET through a second inverter.
Regarding claim 23, Lin does not disclose wherein the current flowing from the second node to the first node is prevented. However, Fu teaches (see Fig. 3) wherein the current flowing from the second node (node of BST2) to the first node (node of BST1) is prevented (diode D1 is configured to prevent current flowing from the node of BST2 to the node of BST1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the current flowing from the second node to the first node is prevented, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor. Regarding claim 24, Lin does not disclose wherein the first diode is configured to prevent reverse flow of the current conducting the direction from the first node to the second node. However, Fu teaches (see Fig. 3) wherein the first diode (D1) is configured to prevent reverse flow of the current conducting the direction from the first node (node of BST1) to the second node (node of BST2) (diode D1 is configured to prevent current flowing from the node of BST2 to the node of BST1). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the first diode is configured to prevent reverse flow of the current conducting the direction from the first node to the second node, as taught by Fu, because it can help implement a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor.
Response to Arguments
Applicant's arguments filed on 12/29/2025 have been fully considered but they are not persuasive. Regarding Claim 1, Applicant argued “the cited references fail to disclose that "the first diode is configured to reduce or prevent current flowing from the second node to the first node," as claimed.”, and further in that “Fu does not disclose that its second diode is configured in any such manner.”. In response to Applicant’s arguments, Examiner points to Fig. 2 of Zeng, which discloses a bidirectional switch SW. The details of implementing the bidirectional switch, i.e. using what components, is not detailed in Fu. However, Fu teaches (see Fig. 3 of Fu) a bidirectional switch 300, wherein the switch comprises a first diode (D1), where it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the converter of Lin wherein the first switch comprises a first diode, as taught by Fu, because it can help implement the bidirectional switch of Fu which can help provide a current blocking function to prevent reverse current flow and to ensure proper desired current flow to charge the targeted bootstrap capacitor. The diode D1 clearly prevents the current from flowing from the nodes BST2 to BST1, which are equivalent to the nodes of BST2 and BST1 of Fu, according to the anode and cathode configuration of D1. Therefore, Applicant’s arguments are not persuasive. Applicant further argued that “since the purpose of the second capacitor and its structure within the circuit are different from those of Fu, it is unclear how a person skilled in the art would easily derive the claimed "first diode" from the first diode (D1) or the second diode (D2) of Fu.” However, the purpose of the second capacitor of the invention is taught by Lin, i.e. C2, which is a bootstrap capacitor that maintains the voltage across the corresponding gate driver DD. Furthermore the capacitor C2 of Lin has CL2 to help maintain the voltage, similar to the claimed invention. On contrary to Applicant’s arguments, Examiner exerts that Fu was introduced as to provide teaching of implementing a bidirectional switch, i.e. SW of Lin, by using a diode, i.e. D1 of Fu, to provide charge sharing between two bootstrap capacitors. Thus Applicant’s arguments are not persuasive.
Conclusion
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/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838