DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of Applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of priority Application No. 10-2022-0173264 filed on December 13, 2022 has been electronically retrieved.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office Action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-9, 11, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0161266 A1 (Shim).
Regarding claim 1, Shim discloses, A semiconductor chip stack structure (FIG. 6) comprising:
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a plurality of first semiconductor chip dies (plurality of first semiconductor chip dies (122); annotated FIG. 6, above; [0043]) stacked in a vertical direction (annotated FIG. 6, above); and
one or more second semiconductor chip dies (one or more second semiconductor chip dies (121); FIG. 6; [0043]) between a predetermined number of first semiconductor chip dies (122) (FIG. 6—second semiconductor chip die (121) is between a predetermined number of first semiconductor chip dies (122)) among the plurality of first semiconductor chip dies (122) directly stacked on top of each other (FIG. 6—first semiconductor chip dies (122) are directly stacked on top of each other) and a remaining number of first semiconductor chip dies (122) among the plurality of first semiconductor chip dies (121) directly stacked on top of each other (FIG. 6—a remaining number of first semiconductor chip dies (122) are directly stacked on top of each other),
wherein a thickness (T2) of each second semiconductor chip die (121) of the one or more second semiconductor chip dies (121) is greater than a thickness (T1) of each first semiconductor chip die (122) of the plurality of first semiconductor chip dies (122) in the vertical direction (annotated FIG. 6, above).
Regarding claim 6, Shim discloses, A semiconductor package (FIG. 6) comprising:
an interposer (interposer (110); FIG. 6; [0043]);
a plurality of semiconductor chip stack structures (plurality of semiconductor chip structures (121 and 122) ; FIG. 6; [0043]) on the interposer (110), each semiconductor chip stack structure (121 and 122) of the plurality of semiconductor chip stack structures (121 and 122) comprising a plurality of first semiconductor chip dies (plurality of first semiconductor chip dies (122); annotated FIG. 6, above; [0043]) stacked in a vertical direction (annotated FIG. 6, above), and one or more second semiconductor chip dies (one or more second semiconductor chip dies (121); FIG. 6; [0043]) between a predetermined number of first semiconductor chip dies (122) (FIG. 6—second semiconductor chip die (121) is between a predetermined number of first semiconductor chip dies (122)) among the plurality of first semiconductor chip dies (122) directly stacked on top of each other (FIG. 6—first semiconductor chip dies (122) are directly stacked on top of each other) and a remaining number of first semiconductor chip dies (122) among the plurality of first semiconductor chip dies (122) directly stacked on top of each other (FIG. 6—a remaining number of first semiconductor chip dies (122) are directly stacked on top of each other);
a third semiconductor chip (third semiconductor chip (150); FIG. 6; [0060]) on the interposer (110); and
an encapsulant (encapsulant (130 and 141); FIG. 6; [0044] and [0047]) on the interposer (110), the plurality of semiconductor chip stack structures (121 and 122), and the third semiconductor chip (150),
wherein a thickness (T2) of each second semiconductor chip die (121) of the one or more second semiconductor chip dies (121) is greater than a thickness (T1) of each first semiconductor chip die (122) of the plurality of first semiconductor chip dies (122) in the vertical direction (annotated FIG. 6, above).
Regarding claim 7, Shim discloses, The semiconductor package (FIG. 6) of claim 6, wherein the third semiconductor chip (150) is adjacent to the plurality of semiconductor chip stack structures (121 and 122) in a horizontal direction (annotated FIG. 6, above).
Regarding claim 8, Shim discloses, The semiconductor package (FIG. 6) of claim 6, wherein the third semiconductor chip (150) is between the plurality of semiconductor chip stack structures (121 and 122) and the interposer (110) (FIG. 6).
Regarding claim 9, Shim discloses, The semiconductor package (FIG. 6) of claim 6, wherein the plurality of semiconductor chip stack structures (121 and 122) comprises a high bandwidth memory (HBM) ([0054]).
Regarding claim 11, Shim discloses, The semiconductor package (FIG. 6) of claim 6, wherein the encapsulant (130 and 141) comprises an epoxy molding compound (EMC) ([0055]).
Regarding claim 12, Shim discloses, A semiconductor package (FIG. 6) comprising:
a substrate (substrate (200); FIG. 6; [0063]);
an interposer (interposer (110); FIG. 6; [0043]);
a plurality of connection members (plurality of connection members (140 and 160); FIG. 6; [0043] and [0044]) electrically connecting the substrate (200) and the interposer (110) ([0044] and [0047]);
a plurality of semiconductor chip stack structures (plurality of semiconductor chip structures (121 and 122) ; FIG. 6; [0043]) directly on the interposer (110), each semiconductor chip stack structure (121 and 122) of the plurality of semiconductor chip stack structures (121 and 122) comprising a plurality of first semiconductor chip dies (plurality of first semiconductor chip dies (122); annotated FIG. 6, above; [0043]) stacked in a vertical direction (annotated FIG. 6, above), and one or more second semiconductor chip dies (one or more second semiconductor chip dies (121); FIG. 6; [0043]) between a predetermined number of first semiconductor chip dies (122) (FIG. 6—second semiconductor chip die (121) is between a predetermined number of first semiconductor chip dies (122)) among the plurality of first semiconductor chip dies (122) directly stacked on top of each other (FIG. 6—first semiconductor chip dies (122) are directly stacked on top of each other) and a remaining number of first semiconductor chip dies (122) among the plurality of first semiconductor chip dies (122) directly stacked on top of each other (FIG. 6—a remaining number of first semiconductor chip dies (122) are directly stacked on top of each other);
a third semiconductor chip (third semiconductor chip (150); FIG. 6; [0060]) on the interposer (110); and
an encapsulant (encapsulant (130 and 141); FIG. 6; [0044] and [0047]) on the interposer (110), the plurality of semiconductor chip stack structures (121 and 122), and the third semiconductor chip (150),
wherein a thickness (T2) of each second semiconductor chip die (121) of the one or more second semiconductor chip dies (121) is greater than a thickness (T1) of each first semiconductor chip die (122) of the plurality of first semiconductor chip dies (122) in the vertical direction (annotated FIG. 6, above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shim, as applied to claim 1, above, in view of US 2022/0352119 A1 (Chang) and further in view of US 2013/0249117 A1 (Lee).
Regarding claim 3, Shim does not appear to explicitly disclose, wherein the thickness of the second semiconductor chip die is 10% or more greater than the thickness of the first semiconductor chip die and is smaller than 55 µm.
However, in analogous art Chang discloses a semiconductor chip stack structure (semiconductor chip stack structure (50); FIG. 5A; [0043]) having a first semiconductor chip die (first semiconductor chip die (501); FIG. 5A; [0043]) with a thickness (thickness (501T); FIG. 5A; [0050]) and a second semiconductor chip die (second semiconductor chip die (502); FIG. 5A; [0043]) with a thickness (thickness (502T); FIG. 5A; [0050]). Chang also discloses that when a thickness difference (502T – 501T) between first and second semiconductor chip dies (501 and 502) is more than 30%, semiconductor chip stack structure (50) is susceptible to warpage and deformation that are caused by uneven stress on the upper surface of first and second semiconductor chip dies (501 and 502) ([0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shim and Chang before him/her that: (i) a thickness difference (T2-T1; annotated FIG. 6, above) between respective second and first semiconductor chip dies (121 and 122) of Shim should be in a range less than or equal 30%, as taught by Chang, to help prevent to warpage and deformation of semiconductor chip stack structure (FIG. 6) of Shim, as also taught by Chang, and (ii) the thickness (T2) of the second semiconductor chip die (121) of Shim is 10% or more greater than the thickness (T1) of the first semiconductor chip die (122) of Shim because this recited range overlaps with the range less than or equal 30% disclosed by Chang. See, MPEP 2144.05(I)—In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
But the combination of Shim in view of Chang does not appear to explicitly disclose, wherein the thickness of the second semiconductor chip die is smaller than 55 µm.
However, in analogous art, Lee discloses that it is well-known that a semiconductor chip die (semiconductor chip die (102); FIG. 5; [0024]) can be predicably formed to have a thickness (thickness (502); FIG. 5; [0061]) in a range of 200 micro meters (µm) or less ([0064]). Lee also that this thickness range is in response to continually increasing demands on information and communication products for ever-reduced thicknesses ([0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shim, Chang, and Lee before him/her that the thickness (T2) of the second semiconductor chip die (121) of Shim in view of Chang is smaller than 55 µm, as taught by Lee, because this claimed range overlaps with the thickness (502) range of 200 micro meters (µm) or less, disclosed by Lee. See, MPEP 2144.05(I), above.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Shim, as applied to claim 1, above, in view of Chang.
Regarding claim 4, Shim does not appear to explicitly disclose, wherein a number of stacked layers of the plurality of first semiconductor chip dies and the one or more second semiconductor chip dies is 12.
However, in analogous art, Chang discloses, a semiconductor chip stack structure (semiconductor chip stack structure (50); FIG. 5A; [0043]) having a plurality of first semiconductor chip dies (plurality of first semiconductor chip dies (501); FIG. 5B; [0050]) and one or more second semiconductor chip dies (one or more second semiconductor chip dies (502); FIG. 5C; [0043]). Chang also discloses that it is well-known that a number of stacked layers of the plurality of first semiconductor chip dies (501) can be predicably fabricated to range between two (2) to ten (10) dies and that a number of stacked layers of the one or more second semiconductor chip dies (502) can be predicably fabricated to range between three (3) to fifteen (15) dies ([0050]). Thus, Chang discloses that the total number of the plurality of first semiconductor chip dies (501) and the one or more second semiconductor chip (502) can range between five (5) to twenty five (25).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shim and Chang before him/her that a number of stacked layers of the plurality of first semiconductor chip dies (122) and the one or more second semiconductor chip dies (121) of Shim is 12, as taught by Chang, because one of ordinary skill in the art would have recognized that there are a finite number of identified, predicable solutions for the number of stacked layers of the first semiconductor chip dies (122) and the one or more second semiconductor chip dies (121) of Shim, as taught by Chang (i.e., between five (5) to twenty five (25)), and, absent unexpected results, it would have been obvious to try each of them (one of which is recited by claim 4) with a reasonable expectation of success. See, MPEP 2143(E)—“Obvious to Try”—Choosing From a Finite Number of Identified, Predicable Solutions, With a Reasonable Expectation of Success.
Regarding claim 5, Shim in view of Chang discloses, The semiconductor chip stack structure of claim 4, wherein a fifth layer ([0050] of Chang) or a seventh layer ([0050] of Chang) from a lowest layer (lowest layer (502a); FIG. 5C; [0047], all of Chang) of the stacked layers comprises the one or more second semiconductor chip dies (502; FIG. 5C; [0047], all of Chang).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shim, as applied to claim 6, above.
Regarding claim 10, Applicant may argue that Shim fails to explicitly disclose, wherein the third semiconductor chip comprises a central processing unit (CPU) or a graphic processing unit (GPU).
However, Shim does disclose that the one or more second semiconductor chip dies (121) may be comprise a graphics processing unit (GPU) ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shim before him/her that the third semiconductor chip (150) of Shim comprises a graphic processing unit (GPU), as taught by Shim, because this is a rearrangement of parts which is an obvious matter of design choice. Please see, MPEP 2144.04(VI)(C).
Claims 13-15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shim, as applied to claim 12, above, in view of US 2020/0135699 A1 (Hwang).
Regarding claim 13, Shim discloses, The semiconductor package (FIG. 6) of claim 12, wherein a first semiconductor chip die (a first semiconductor chip die (122); FIG. 6; [0043]) among the plurality of first semiconductor chip dies (122) comprises a plurality of first bonding pads (plurality of first bonding pads (122P); FIG. 6; [0043])) . . . on at least one of an upper surface (annotated FIG. 6, above) of the first semiconductor chip die (122) and a lower surface (annotated FIG. 6, above) of the first semiconductor chip die (122) in a horizontal direction (annotated FIG. 6, above), and
wherein a second semiconductor chip die (second semiconductor chip die (121); FIG. 6; [0043]) among the one or more second semiconductor chip dies (121) comprises a plurality of second bonding pads (plurality of second bonding pads (121P); FIG. 6; [0043]) . . . on a lower surface (annotated FIG. 6, above) of the second semiconductor chip die (121) in the horizontal direction (annotated FIG. 6, above).
But, Shim does not appear to explicitly disclose,
wherein a first semiconductor chip die among the plurality of first semiconductor chip dies comprises a first insulating layer at a same level as the plurality of first bonding pads on at least one of an upper surface of the first semiconductor chip die and a lower surface of the first semiconductor chip die in a horizontal direction, and
wherein a second semiconductor chip die among the one or more second semiconductor chip dies comprises a second insulating layer at a same level as the plurality of second bonding pads on each of an upper surface of the second semiconductor chip die and a lower surface of the second semiconductor chip die in the horizontal direction.
However, in analogous art, Hwang discloses, that it is well-known that a semiconductor package (semiconductor package (300B); FIG. 3; [0043]) can be predicably fabricated to include a semiconductor chip stack structure (semiconductor chip stack structure (100A-100D); FIG. 3; [0021]) on an interposer (interposer (200); FIG. 3; [0047]). Hwang also discloses that it is well-known that semiconductor chip stack structure (100A-100D) can be predicably fabricated to include a plurality of first semiconductor chip dies (plurality of first semiconductor chip dies (100A) and (100C); annotated FIG. 3, below) and one or more second semiconductor chip dies (one or more second semiconductor chip dies (100B); annotated FIG 3, below) between adjacent first semiconductor chip dies (100A and 100C) among the plurality of semiconductor chip dies (100A-100D). Hwang additionally discloses that it is well-known that first semiconductor chip die (100C) can be predicably formed to include a plurality of first bonding pads (first bonding pads (152); FIG. 3; [0021]) on a lower surface (annotated FIG. 3, below) thereof and a plurality of first bonding pads (154); FIG. 3; [0021]) on an upper surface (annotated FIG. 3, below) thereof and second semiconductor chip die (100B) can be predicably formed to include a plurality of second bonding pads (second bonding pads (152); FIG. 3; [0021]) on a lower surface (annotated FIG. 3, below) thereof and a plurality of second bonding pads (154); FIG. 3; [0021]) on an upper surface (annotated FIG. 3, below) thereof in a horizontal direction (annotated FIG. 3, below). Hwang further discloses that boding pads (152 and 154) electrically connect first semiconductor chip die (100C) and second semiconductor chip die (102B) together, as well as semiconductor chip dies (100A and 100D) ([0025]).
Hwang also further discloses that it is well-known that semiconductor package (300B) may be predicably formed to include a bonding structure (bonding structure (BS); FIG. 3; [0028]) having a first insulating layer (first insulating layer (162); FIG. 3; [0028]) formed at a same level as the plurality of first bonding pads (152) on the lower surface (annotated FIG. 3, below) of first semiconductor chip die (100C) in a horizontal direction, a first insulating layer (first insulating layer (164); FIG. 3; [0028]) at a same level as the plurality of first bonding pads (154) on the upper surface (annotated FIG. 3, below) of first semiconductor chip die (100C) in a horizontal direction, a second insulating layer (second insulating layer (162); FIG. 3; [0028]) at a same level as the plurality of second bonding pads (152) on the lower surface (annotated FIG. 3, below) of second semiconductor chip die (100B) in a horizontal direction, and a second insulating layer (second insulating layer (164); FIG. 3; [0028]) at a same level as the plurality of second bonding pads (154) on the upper surface (annotated FIG. 3, below) of second semiconductor chip die (100B) in a horizontal direction. Hwang additionally further discloses that bonding structure (BS) may implement firm hybrid-bonding by directly bonding insulation layers (162 and 164) which firmly bonds stacked first semiconductor chip die (100C) and second semiconductor chip die (100B) together and a direct metal bonding structure in which bonding of pads (152 and 154) are directly bonded ([0031] and [0041]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shim and Hwang before him/her that a first semiconductor chip die (122) among the plurality of first semiconductor chip dies (122) of Shim comprises a plurality of first bonding pads (122P) and a first insulating layer at a same level as the plurality of first bonding pads (122P) on at least one of an upper surface of the first semiconductor chip die (122; annotated FIG. 6, above) and a lower surface of the first semiconductor chip die (122; annotated FIG. 6, above) in a horizontal direction (annotated FIG. 6, above), as taught by Hwang, and that the second semiconductor chip die (121) comprises a plurality of second bonding pads (121P) and a second insulating layer at a same level as the plurality of second bonding pads (121P) on each of an upper surface of the second semiconductor chip die (121; annotated FIG. 6, above) and a lower surface of the second semiconductor chip die (121; annotated FIG. 6, above) in the horizontal direction (annotated FIG. 6, above), as also taught by Hwang, thereby creating a bonding structure that implements a firm hybrid-bonding by directly bonding the first and second insulation layers of semiconductor chip stack structure (121 and 122) to interposer (110) of Shim and a direct metal bonding structure in which respective first and second bonding of pads (122P and 121P) of semiconductor chip stack structure (121 and 122) are directly bonded to interposer (110) of Shim, as additionally taught by Hwang.
Regarding claim 14, Shim in view of Hwang discloses, The semiconductor package (FIG. 6 of Shim) of claim 13, wherein each first bonding pad (152 or 154, both of Hwang) of the plurality of first bonding pads (152 and 154, both of Hwang) of the first semiconductor chip die (122 of Shim) or each second bonding pad (152 or 154, both of Hwang) of the plurality of second bonding pads (152 and 154, both of Hwang) of the second semiconductor chip die (121 of Shim) is directly on each first bonding pad (152 or 154; annotated FIG. 3, above, all of Hwang) of a plurality of first bonding pads (152 and 154, both of Hwang) of an adjacent first semiconductor chip die (122 of Shim) or each second bonding pad (152 or 154; annotated FIG. 3, above, all of Hwang) of a plurality of second bonding pads (152 and 154, both of Hwang) of an adjacent second semiconductor chip die (121 of Shim).
Regarding claim 15, Shim in view of Hwang discloses, The semiconductor package (FIG. 6 of Shim) of claim 14, wherein the first insulating layer (162 or 164, both of Hwang) included in the first semiconductor chip die (122 of Shim) or the second insulating layer (162 or 164, both of Hwang) included in the second semiconductor chip die (121 of Shim) is directly on a first insulating layer (162 or 164; annotated FIG. 3, above, all of Hwang) of an adjacent first semiconductor chip die (122 of Shim) or a second insulating layer (162 or 164; annotated FIG. 3, above, all of Hwang) of an adjacent second semiconductor chip die (121 of Shim).
Regarding claim 19, Shim in view of Hwang discloses, The semiconductor package (FIG. 6 of Shim) of claim 13, wherein the first insulation layer (162 and 164, both of Hwang) and the second insulation layer (162 and 164, both of Hwang) comprise silicon oxide ([0028] of Hwang).
Regarding claim 20, Shim in view of Hwang discloses, The semiconductor package (FIG. 6 of Shim) of claim 13, wherein the plurality of first bonding pads (122P of Shim) and the plurality of second bonding pads (121P of Shim) comprise copper (Cu) ([0051] of Shim).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Hwang, as applied to claim 13, above, and further in view of US 2020/0168554 A1 (Fay).
Regarding claim 16, Shim in view of Hwang does not appear to explicitly disclose, wherein the interposer comprises a silicon interposer.
However, in analogous art, Fay discloses, that it is well-known that a semiconductor assembly (semiconductor assembly (100); FIG. 1A; [0022]) may be predicably formed to include an interposer (interposer (106); FIG. 1A; [0022]), a plurality of semiconductor chip stack structures (plurality of semiconductor chip stack structures (104A-104D); FIG. 1A; [0022])) directly on interposer (106) and that comprise a plurality of first semiconductor chip dies stacked in a vertical direction (annotated FIG. 1A, below) and one or more second semiconductor chip dies between adjacent first semiconductor chip dies (annotated FIG. 1A, below). Fay also discloses that it is well-known that semiconductor assembly (100) may be predicably formed to include a third semiconductor chip (third semiconductor chip (102); FIG. 1A; [0022]) on interposer (106). Fay additionally discloses that it is well-known that silicon interposers benefit from being processed by conventional semiconductor methods and can provide tighter line spacing capability ([0008]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Shim, Hwang, and Fay before him/her that interposer (110) of Shim in view of Hwang comprise silicon, as taught by Fay, to benefit from being processed by conventional semiconductor methods and to provide tighter line spacing capability, as also taught by Fay.
Regarding claim 17, Shim in view of Hwang and further in view of Fay discloses, The semiconductor package (FIG. 6 of Shim) of claim 16, wherein the silicon interposer (110) comprises a plurality of third bonding pads (third bonding pads (113); FIG. 6; [0046], all of Shim) and a third insulating layer (third insulating layer (111); FIG. 6; [0046], all of Shim).
Regarding claim 18, Shim in view of Hwang and further in view of Fay discloses, The semiconductor package (FIG. 6 of Shim) of claim 17, wherein each third bonding pad (113 of Shim) of the plurality of third bonding pads (113 of Shim) included in the silicon interposer (110 of Shim) is directly on each first bonding pad (152 of Hwang) of the plurality of first bonding pads (152 of Hwang) on a lower surface of the first semiconductor chip die (first semiconductor chip die (100A); annotated FIG. 3, above; [0021], all of Hwang) at a lowermost end of the plurality of first semiconductor chip dies (122; annotated FIG. 6, above) of each semiconductor chip stack structure (121 and 122 of Shim) of the plurality of semiconductor chip stack structures (121 and 122), and
wherein the third insulating layer (111 of Shim) included in the silicon interposer (110 of Shim) is directly on the first insulating layer (164; annotated FIG. 3, above, both of Hwang) of the lower surface of the first semiconductor chip die at the lowermost end (122; annotated FIG. 6, both of Shim).
Response to Arguments and Amendments
Applicant’s amendment of paragraph [0095] of the specification and remarks on page 14 of the “Amendment Under 37 C.F.R. § 1.111” dated February 27, 2026 (hereinafter the “Reply”) have overcome the objection to the drawings in the Office Action dated December 1, 2025 (hereinafter the “Office Action”). Also, Applicant’s amendment of claims 3 and 18 and remarks on page 14 of the Reply have overcome the objection to claims 3 and 18 in the Office Action. Additionally, Applicant’s amendment of independent claims 1, 6, and 12, and remarks on pages 15-17 of the Reply have been fully considered. However, they are deemed moot given the new grounds of rejection of independent claims 1, 6, and 12 in this Final Office Action which were necessitated by Applicant’s amendment thereof in the Reply.
Notwithstanding the above, in an effort to advance prosecution, the Examiner respectfully requests that Applicant please consider initiating a telephone interview with the Examiner to discuss amendments that Applicant would like to propose to overcome the rejection of claims 1 and 3-19 in this Final Office Action prior to submitting a written response thereto. The Examiner would welcome such a conversation and is available at the telephone number indicated below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights