DETAILED ACTION
The instant application having Application No. 18/220,206 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 252, 254, and 256 in FIG. 2; 704 in FIG. 7; 942 in FIG. 9A; 1050 and 1072 in FIG. 10; 886 in FIG. 11. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: apparatus in claims 1-10.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 11-12, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Davis et al. (Publication Number US 2016/0179717 A1).
As per claim 1, Davis et al. discloses “An apparatus comprising: a system within a package (system-on-chip (SoC); FIG. 2-3) comprising: a communication fabric and circuitry to adjust a packet throughput rate associated with the communication fabric based at least in part on incoming receive rate across multiple input ports and fabric usage (the host system 112 may be configured to provide a range of virtual instance types (e.g., small computing, big computing, small networking, big networking, etc.) that may require reconfiguration of different subsystems for each of the virtual server instances to match the needed resources to the throughput requirement of the server instance [Paragraph 0050]. The reconfigurable last level cache resources 212 may be dynamically repartitioned with the reconfigurable processing cores 302 and the reconfigurable memory resources 208 between the network compute subsystem 104 and the server compute subsystem 108 based on the memory and bandwidth requirement of the configured processing cores for each compute subsystem; Paragraph 0053), wherein: the communication fabric is to communicatively couple devices in the package including one or more of: an accelerator (acceleration unit 216; FIG. 3), a processor (processing cores 302; FIG. 3), a memory (see the memory controllers 308; FIG. 3), or a network interface device (network I/O subsystem; FIG. 3).”
As per claim 4, Davis et al. discloses “The apparatus of claim 1 (as disclosed by Davis et al. above), wherein the communication fabric comprises at least one ingress port, the at least one ingress port is to receive the packet from the circuitry, and the circuitry comprises at least one timing pacing circuitry per ingress port (timing resources; Paragraph 0030).”
As per claim 11, Davis et al. discloses “A non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: enable timed pacing circuitry to adjust a packet throughput rate associated with a communication fabric based at least in part on incoming receive rate across multiple input ports and fabric usage (the host system 112 may be configured to provide a range of virtual instance types (e.g., small computing, big computing, small networking, big networking, etc.) that may require reconfiguration of different subsystems for each of the virtual server instances to match the needed resources to the throughput requirement of the server instance [Paragraph 0050]. The reconfigurable last level cache resources 212 may be dynamically repartitioned with the reconfigurable processing cores 302 and the reconfigurable memory resources 208 between the network compute subsystem 104 and the server compute subsystem 108 based on the memory and bandwidth requirement of the configured processing cores for each compute subsystem; Paragraph 0053), wherein: the communication fabric and the timed pacing circuitry are enclosed within a package and the communication fabric is to communicatively couple devices in the package including one or more of: an accelerator (acceleration unit 216; FIG. 3), a processor (processing cores 302; FIG. 3), a memory (see the memory controllers 308; FIG. 3), or a network interface device (network I/O subsystem; FIG. 3).”
As per claim 12, Davis et al. discloses “The non-transitory computer-readable medium of claim 11 (as disclosed by Davis et al. above), wherein to adjust the packet throughput rate of the communication fabric comprises control of an ingress rate of packets into the communication fabric (timing resources; Paragraph 0030).”
As per claim 17, Davis et al. discloses “A method comprising: for a communications fabric for devices within a package: adjusting a packet throughput rate associated with the communication fabric based at least in part on incoming receive rate across multiple input ports and fabric usage (the host system 112 may be configured to provide a range of virtual instance types (e.g., small computing, big computing, small networking, big networking, etc.) that may require reconfiguration of different subsystems for each of the virtual server instances to match the needed resources to the throughput requirement of the server instance [Paragraph 0050]. The reconfigurable last level cache resources 212 may be dynamically repartitioned with the reconfigurable processing cores 302 and the reconfigurable memory resources 208 between the network compute subsystem 104 and the server compute subsystem 108 based on the memory and bandwidth requirement of the configured processing cores for each compute subsystem; Paragraph 0053), wherein the communication fabric is to communicatively couple devices in the package including one or more of: an accelerator (acceleration unit 216; FIG. 3), a processor (processing cores 302; FIG. 3), a memory (see the memory controllers 308; FIG. 3), or a network interface device (network I/O subsystem; FIG. 3).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 2, 6-9, 14-16, and 19-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Davis et al. (Publication Number US 2016/0179717 A1) in view of Buskirk et al. (Patent Number US 7,453,892 B2).
As per claim 2, Davis et al. discloses “The apparatus of claim 1 (as disclosed by Davis et al. above).” While Davis et al. discloses setting throughput [Paragraphs 0050 and 0053], Davis et al. does not disclose the mechanism of controlling ingress/egress as disclosed in the limitation “wherein the circuitry is to adjust the packet throughput rate of the communication fabric by control of an ingress rate of packets into the communication fabric.”
Buskirk et al. discloses the mechanism of controlling ingress/egress as disclosed in the limitation “wherein the circuitry is to adjust the packet throughput rate of the communication fabric by control of an ingress rate of packets into the communication fabric (ingress processing; Claim 1).”
Davis et al. and Buskirk et al. are analogous art in that they in the field of data throughput control.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Buskirk et al. for policing packets of multiple transmission protocols [Column 3, lines 42-46].
As per claim 6, Davis et al. discloses “The apparatus of claim 1 (as disclosed by Davis et al. above).” However, Davis et al. does not disclose “comprising: circuitry to adjust utilization of a core based on detection of a burst in packet traffic.”
Buskirk et al. discloses “comprising: circuitry to adjust utilization of a core based on detection of a burst in packet traffic (burst regulated policing methodology; Column 13, lines 40-67).”
Davis et al. and Buskirk et al. are analogous art in that they in the field of data throughput control.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Buskirk et al. for policing packets of multiple transmission protocols [Column 3, lines 42-46].
As per claims 7 and 16, Davis et al. discloses “The apparatus of claim 6 (as disclosed by Davis et al. and Buskirk et al. above), wherein the detection of a burst in packet traffic is based on detected repeated changes relative to a level of power and/or frequency of a core, accelerator, or network interface device that processes the packet traffic (power and timing; Paragraph 0030).”
As per claim 8, Buskirk et al. discloses “The apparatus of claim 6 (as disclosed by Davis et al. and Buskirk et al. above), wherein the adjust utilization of a core based on a burst in packet traffic comprises one or more of: add additional processor capacity to process packets, disable core frequency management, migrate data processing thread to another core, notify a network interface device to route a percentage of received network traffic to a different one or more receive queues, notify a data-plane application to forward a percentage of network traffic to a polling thread running on another core, or raise an alarm to identify a bursty network interface (burst regulated policing methodology [Column 13, lines 40-67]. Emphasis on ‘one or more of’ where one, but not all, of the following could be used).”
As per claim 9, Davis et al. discloses “The apparatus of claim 6 (as disclosed by Davis et al. and Buskirk et al. above), wherein the package comprises the accelerator (acceleration unit 216; FIG. 3), the processor (processing cores 302; FIG. 3), a memory (see the memory controllers 308; FIG. 3), and the network interface device (network I/O subsystem; FIG. 3).”
As per claim 14, Davis et al. discloses “The non-transitory computer-readable medium of claim 11 (as disclosed by Davis et al. above).” However, Davis et al. does not disclose ‘wherein at least one packet comprises one or more of: a network packet, a Peripheral Component Interconnect Express (PCIe) Transaction Layer Packet (TLP) packet, or a cache line size data.”
Buskirk et al. discloses “wherein at least one packet comprises one or more of: a network packet, a Peripheral Component Interconnect Express (PCIe) Transaction Layer Packet (TLP) packet, or a cache line size data (Abstract, lines 1-3; Column 1, lines 53-60).”
Davis et al. and Buskirk et al. are analogous art in that they in the field of data throughput control.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Buskirk et al. for policing packets of multiple transmission protocols [Column 3, lines 42-46].
As per claim 15, Davis et al. discloses “The non-transitory computer-readable medium of claim 11 (as disclosed by Davis et al. above).” However, Davis et al. does not disclose “comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: enable circuitry to adjust utilization of a core based on detection of a burst in packet traffic.”
Buskirk et al. discloses “comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: enable circuitry to adjust utilization of a core based on detection of a burst in packet traffic (burst regulated policing methodology; Column 13, lines 40-67).”
Davis et al. and Buskirk et al. are analogous art in that they in the field of data throughput control.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Buskirk et al. for policing packets of multiple transmission protocols [Column 3, lines 42-46].
As per claim 19, Davis et al. discloses “The method of claim 17 (as disclosed by Davis et al. above).” However, Davis et al. does not disclose “wherein at least one packet comprises one or more of: an Ethernet packet, a Peripheral Component Interconnect Express (PCIe) Transaction Layer Packet (TLP) packet, or a cache line size data.”
Buskirk et al. discloses “wherein at least one packet comprises one or more of: an Ethernet packet, a Peripheral Component Interconnect Express (PCIe) Transaction Layer Packet (TLP) packet, or a cache line size data (Abstract, lines 1-3; Column 1, lines 53-60).”
Davis et al. and Buskirk et al. are analogous art in that they in the field of data throughput control.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Buskirk et al. for policing packets of multiple transmission protocols [Column 3, lines 42-46].
As per claim 20, Davis et al. discloses “The method of claim 17 (as disclosed by Davis et al. above).” However, Davis et al. does not disclose “comprising: adjusting utilization of a core based on detection of a burst in packet traffic.”
Buskirk et al. discloses “comprising: adjusting utilization of a core based on detection of a burst in packet traffic (burst regulated policing methodology; Column 13, lines 40-67).”
Davis et al. and Buskirk et al. are analogous art in that they in the field of data throughput control.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Buskirk et al. for policing packets of multiple transmission protocols [Column 3, lines 42-46].
Claims 3, 5, 13, and 18 are rejected under 35 U.S.C. 103(a) as being unpatentable over Davis et al. (Publication Number US 2016/0179717 A1) in view of Van Doren et al. (Publication Number US 2003/0076831 A1).
As per claims 3, 13, and 18, Davis et al. discloses “The apparatus of claim 1 (as disclosed by Davis et al. above).” While Davis et al. discloses “wherein the communication fabric includes a physical interconnect (reconfigurable I/O resources 210 connected to the host system; FIG. 1), a bridge (fabric bridge; FIG. 2), Caching Agents (Paragraph 0050),” Davis et al. does not disclose “Home Agents, snoop filters, and queues.”
Van Doren et al. discloses “Home Agents (‘home’ QBB node; Paragraph 0034), snoop filters (Paragraph 0037), and queues (Paragraph 0042).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Van Doren et al. to allow efficient balancing between bandwidth consumption and channel progress in a multiprocessor system [Paragraph 0008].
As per claim 5, Davis et al. discloses “The apparatus of claim 1 (as disclosed by Davis et al. above).” However, Davis et al. does not disclose “wherein the circuitry comprises at least one queue to enqueue packets and delay dequeue packets until specified times.”
Van Doren et al. discloses “wherein the circuitry comprises at least one queue to enqueue packets and delay dequeue packets until specified times (Paragraphs 0059, 0062, and 0066-0067).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Van Doren et al. to allow efficient balancing between bandwidth consumption and channel progress in a multiprocessor system [Paragraph 0008].
Claim 10 is rejected under 35 U.S.C. 103(a) as being unpatentable over Davis et al. (Publication Number US 2016/0179717 A1) in view of Stimac (Patent Number US 7,334,033 B2).
As per claim 10, Davis et al. discloses “The apparatus of claim 1 (as disclosed by Davis et al. above).” However, Davis et al. does not disclose “wherein based on a level of the communication fabric, the circuitry is to be disabled from performance of adjustment of packet throughput rate associated with the communication fabric.”
Stimac discloses “wherein based on a level of the communication fabric, the circuitry is to be disabled from performance of adjustment of packet throughput rate associated with the communication fabric (Column 1, lines 57-67 to Column 2, lines 1-6).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Davis et al. and Stimac for accommodating indeterminate fabric states which may be encountered [Column 2, lines 3-6].
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated October 16, 2024, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach throughput settings.
U.S. PATENT NUMBERS:2012/0072631 A1 – [Paragraph 0022]
11,677,662 B2
11,681,349 B2
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.W.Y/Examiner, Art Unit 2181 September 30, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
