DETAILED ACTION
This action is in response to the claims filed 07/10/2023 for Application number 18/220,212. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Khammassi ("US 20210182071 A1", hereinafter "Khammassi") in view of Fu et al. ("eQASM:AnExecutable Quantum Instruction Set Architecture", hereinafter "Fu").
Regarding claim 1, Khammassi teaches A quantum control processor (¶0035) comprising:
instruction fetch logic to fetch instructions from a memory, the instructions including quantum instructions (“FIG. 2 illustrates one embodiment of a processor or core 210 which fetches, decodes, and executes quantum instructions 201A” [¶0038]);
decode logic to decode the quantum instructions into a first plurality of quantum microoperations; (“A decoder 202 decodes the instructions 201A-B into micro-operations or uops 203A which are scheduled for execution by a scheduler 203 and executed by execution circuitry 204.” [¶0040])
translation logic to translate the first plurality of quantum microoperations into a second plurality of quantum microoperations (See ¶0058, “direct digital synthesis (DSS) core block which translates a new set of instructions or microoperations (uops) into pulses used to control qubits of a quantum processor.”)
and
issue logic to synchronously issue the second plurality of quantum microoperations to the plurality of quantum controller cores in parallel (“For example, to maximize parallelization, the dispatch/timing control circuitry 706 may maintain a first quantum operation on the same core as a second quantum operation which is dependent on the results of the first quantum operation. In contrast, quantum operations which are not dependent may be distributed to different cores, to allow for parallel execution.” [¶0065]).
However fails to explicitly teach translation logic to translate the first plurality of quantum microoperations into a second plurality of quantum microoperations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor
Fu teaches translation logic to translate the first plurality of quantum microoperations into a second plurality of quantum microoperations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor (“Hence, the micro-operations should be reorganized into device operations to trigger the corresponding devices. The device event distributor reorganizes multiple micro-operations associated with the same timing label into different device operations.” [pg. 234, left col, ¶1; See further Fig 10 and pg. 230 further discloses “The VLIW width of eQASM characterizes the number of quantum operations that can be put in a single instruction word, which is defined during eQASM instantiation.”]);
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Khammassi’s teachings by translating a first plurality of quantum micro-ops into a second plurality of quantum micro-ops based on characteristics of quantum controller cores as taught by Fu. One would have been motivated to make this modification in order to propose an executable QISA that can be translated from quantum assembly language that supports comprehensive quantum program flow control. [Abstract, Fu]
Regarding claim 2, Khammassi/Fu teaches The quantum control processor of claim 1 where Khammassi teaches wherein the instructions further include non-quantum instructions, wherein the decode logic is to decode the non-quantum instructions into a plurality of non- quantum microoperations (“For example, quantum decode circuitry 202A may be added to the decoder 202 for decoding the quantum instructions 201A, just as non-quantum decode circuitry 202B decodes non-quantum instructions 201B.” [¶0040]), the quantum control processor further comprising:
dispatch logic to dispatch the plurality of non-quantum microoperations to one or more execution units and to dispatch the first plurality of quantum microoperations to the translation logic. (“The quantum and non-quantum uops 203A generated by the decoder 202 may initially be queued for execution within one or more uop queues of the scheduler 203, which dispatches the uops from the uop queue(s) in accordance with dependencies and/or execution resource availability.” [¶0042])
Regarding claim 3, Khammassi/Fu teaches The quantum control processor of claim 1 where Khammassi teaches wherein the translation logic comprises a plurality of translation units, each translation unit associated with a quantum controller core of the plurality of quantum controller cores and configured to translate one or more of the first plurality of quantum microoperations into one or more of the second plurality of quantum microoperations for execution by the quantum controller core. (“The resulting quantum microoperations are dispatched to the various cores 790A-C by dispatch/timing control circuitry 706. In one embodiment, the dispatch/timing control circuitry 706 distributes the quantum uops 720A-C to the different cores 790A-C based on uop data and/or resource dependencies. For example, to maximize parallelization, the dispatch/timing control circuitry 706 may maintain a first quantum operation on the same core as a second quantum operation which is dependent on the results of the first quantum operation. In contrast, quantum operations which are not dependent may be distributed to different cores, to allow for parallel execution.” [¶0065])
Regarding claim 4, Khammassi/Fu teaches The quantum control processor of claim 3, where Khammassi teaches wherein the issue logic comprises a plurality of issue queues, each issue queue corresponding to a translation unit of the plurality of translation units and configured to store the one or more quantum microoperations of the first plurality of quantum microoperations or an indication of the one or more quantum microoperations of the first plurality of quantum microoperations. (“The circuitry in FIG. 8 may be included in a set of Direct Digital Synthesis (DDS) cores (e.g., such as in the arrangement in FIG. 7) to generate per-channel signals with frequencies ranging from DC (0 Hz) to a configurable high frequency (the highest frequency bound is configurable and depends mainly on the speed of the used DAC). Each such channel may have its own microinstruction queue as shown in FIG. 7, from which microinstructions are executed according to the specified timing.” [¶0073; See also ¶0065 discloses multiple cores])
Regarding claim 5, Khammassi/Fu teaches The quantum control processor of claim 1, where Khammassi teaches further comprising:
a configuration memory to store configuration data related to the characteristics of the plurality of quantum controller cores (“These operations will synthesize the qubit control pulses based on the waveform parameters encoded in the instruction and the various correction parameters specified via a configuration interface 805. (“configuration memory”)” [¶0073]), wherein the decode logic is to read the configuration data to identify a first quantum controller core of the plurality of quantum controller cores to execute one or more microoperations of the second plurality of quantum microoperations associated with a first instruction of the plurality of quantum instructions. (“Thus, the circuit shown in FIG. 8 is capable of performing signal synthesis for each specific qubit based on operations specified in a decoded microinstruction.” [¶0073])
Regarding claim 6, Khammassi/Fu teaches The quantum control processor of claim 5 further comprising: Khammassi teaches calibration logic to execute one or more calibration routines to generate at least a portion of the configuration data. (“In addition, due to limited memory resources, calibration routines may be slowed down by uploading the waveform partially at each step.” [¶0054])
Regarding claim 7, Khammassi/Fu teaches The quantum control processor of claim 1 Khammassi teaches further comprising at least one of a modular front end unit comprising the instruction fetch logic and decode logic (See FIG. 3, “FIG. 3 illustrates an embodiment of front-end circuitry of a processor for processing quantum and non-quantum instructions” [¶0007; 202A-B 302A-B, 301 A Prefetch buffers]) and
a modular back end unit comprising the translation logic and issue logic (See FIG. 2, 204E Quantum Engine Functional Units), the quantum control processor further comprising:
a modular interface to couple a variable number of modular front end units or modular back end units. (See FIG 2., Front-end circuitry is connected to Quantum Engine Functional Units 204E)
Regarding claim 9, Khammassi/Fu teaches The quantum control processor of claim 1 Khammassi teaches wherein the translation logic is to store the second plurality of quantum microoperations in a memory (See ¶0048, “he operands for the quantum and non-quantum uops are stored in a set of shared registers 321 (as described above) and accessed by the quantum functional units 320 when executing the uops”), the quantum control processor further comprising:
a quantum controller manager to communicate with the issue logic to cause the plurality of quantum controller cores to access a respective portion of the second plurality of quantum microoperations from a respective region of the memory. (“Each such channel may have its own microinstruction queue as shown in FIG. 7, from which microinstructions are executed according to the specified timing.” [¶0073; storing each microinstruction into channel would include the need to access a portion of microoperations from a respective region of the memory.])
Regarding claim 10, Khammassi/Fu teaches The quantum control processor of claim 9 further comprising:
Khammassi teaches timing circuitry coupled to the issue logic and the quantum controller manager, the issue logic and/or the quantum controller manager to access the timing circuitry to synchronously issue the second plurality of quantum microoperations in parallel to the plurality of quantum controller cores. (“In one embodiment, the dispatch/timing control circuitry 706 distributes the quantum uops 720A-C to the different cores 790A-C based on uop data and/or resource dependencies. For example, to maximize parallelization, the dispatch/timing control circuitry 706 may maintain a first quantum operation on the same core as a second quantum operation which is dependent on the results of the first quantum operation. In contrast, quantum operations which are not dependent may be distributed to different cores, to allow for parallel execution.” [¶0065])
Regarding claim 11, it is substantially similar to claim 1 respectively, and is rejected in the same manner, the same art, and reasoning applying.
Regarding claims 12-17, they are substantially similar to claims 2-6 and 9 respectively, and are rejected in the same manner, the same art, and reasoning applying.
Regarding claim 18, it is substantially similar to claims 1 and 11 respectively, and is rejected in the same manner, the same art, and reasoning applying.
Regarding claims 19 and 20, they are substantially similar to claims 2 and 3 respectively, and are rejected in the same manner, the same art, and reasoning applying.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Khammassi in view of Fu and further in view of Latorre et al. ("US 20050262270 A1", hereinafter "Latorre").
Regarding claim 8, Khammassi/Fu teaches The quantum control processor of claim 1 further comprising: however fails to explicitly teach a modular cluster comprising a front end unit and zero or more additional front end units and a back end unit and zero or more additional back end units.
Latorre teaches a modular cluster comprising a front end unit and zero or more additional front end units and a back end unit and zero or more additional back end units. (“The plurality of clusters 102 may be comprised of a plurality of front-end units 104.sub.1, 104.sub.2, . . . , 104.sub.n and a plurality of back-end units 106.sub.1, 106.sub.2, 106.sub.3, 106.sub.4, 106.sub.5, 106.sub.6, . . . , 106.sub.m.” [¶0014])
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Khammassi’s/Fu’s teachings in order to implement a multithreaded clustered microarchitecture with clusters of front-end and back-end units as taught by Latorre. One would have been motivated to make this modification as clustering allows processors to be divided into simpler components while reducing local wire delays to meet increasing microprocessor frequency demands. [¶0004, Latorre]
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zou et al. (“US 20190042970 A1”) discloses a hybrid classical quantum processor to decode quantum and non-quantum instructions
Zhang et al. (“US 20220327413 A1”) discloses a quantum control system and instruction execution method which includes a schedular, an instruction memory, and a plurality of processing units.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL H HOANG whose telephone number is (571)272-8491. The examiner can normally be reached Mon-Fri 8:30AM-4:30PM.
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/MICHAEL H HOANG/ PRIMARY EXAMINER, Art Unit 2122
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