Attorney Docket Number: 2207014US
Filing Date: 7/10/2023
Claimed Foreign Priority Date: 7/12/2022 (TW111126109)
Inventors: Yu et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed on 7/20/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendment filed 7/20/2026, responding to the office action mailed on 4/20/2026, has been entered. Applicant amended claims 1, 8, 11, and 13-14. The present office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims have overcome most of the respective claim rejection under 35 U.S.C. 112, as previously formulated in the Non-Final Office action mailed on 4/20/2025. Accordingly, pending in this application are claims 1-8 and 11-14. New grounds of rejections are presented below, however, upon further consideration of the claims.
Claim Objections
Claim 1 is objected to because of the following informalities: “…an eighth surface…” is already recited earlier within the claim (see line 28 “…and an eighth surface…”). For the purpose of examination, the second recitation of “…an eighth surface…” recitation of claim 8 will be construed to recite “…the eighth surface…”. Appropriate correction is required.
Claim 11 is objected to because of the following informalities: “…as in claims 1…” is improper. For the purpose of examination, the line will be construed to recite “…as in claim 1…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Applicant is encouraged to review ALL claims for consistency.
Claim 1 recites the limitation “…the rest part of the axial connecting circuit…” in line 42. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the rest part of the axial connecting circuit…” will be construed to recite “…a remaining part of the axial connecting circuit…”.
Claim 1 also recites the limitation “…the groove…” in line 11. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the groove…” will be construed to recite “…the at least one groove…”.
Claim 1 also recites the limitation “…the first dielectric layer…” in lines 9, 11, 13, and 14. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the first dielectric layer…” will be construed to recite “…the at least one first dielectric layer…”.
Claim 1 also recites the limitation “…the bump…” in line 15. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the bump…” will be construed to recite “…the at least one bump…”.
Claim 1 also recites the limitation “…the first conductive circuit…” in lines 7-8 and 36. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the first conductive circuit…” will be construed to recite “…the at least one first conductive circuit…”.
Claim 1 also recites the limitation “…the die pad…” in lines 10 and 12. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the die pad…” will be construed to recite “…the at least one die pad…”.
Claim 1 also recites the limitation “…the second conductive circuit…” in lines 20, 23, 27, and 37. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the second conductive circuit…” will be construed to recite “…the at least one second conductive circuit…”.
Claim 1 also recites the limitation “…the third dielectric layer…” in line 12. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the third dielectric layer…” will be construed to recite “…the at least one third dielectric layer…”.
Claim 1 also recites the limitation “…the first circuit layer…” in lines 23 and 44. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the first circuit layer…” will be construed to recite “…the at least one first circuit layer…”.
Claim 1 also recites the limitation “…the second dielectric layer…” in lines 18-20. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the second dielectric layer…” will be construed to recite “…the at least one second dielectric layer…”.
Claim 1 also recites the limitation “…the first lateral side…” in lines 24 and 33. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the first lateral side…” will be construed to recite “…the at least one first lateral side…”.
Claim 1 also recites the limitation “…the second lateral side…” in lines 24 and 34. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the second lateral side…” will be construed to recite “…the at least one second lateral side…”.
Claim 1 also recites the limitation “…the third lateral side…” in lines 24 and 34. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the third lateral side…” will be construed to recite “…the at least one third lateral side…”.
Claim 2 recites the limitation “…the first conductive circuit…” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the first conductive circuit…” will be construed to recite “…the at least one first conductive circuit…”, as in claim 1.
Claim 3 recites the limitation “…the second conductive circuit…” in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the second conductive circuit…” will be construed to recite “…the at least one second conductive circuit…”, as in claim 1.
Claim 4 recites the limitation “…the third dielectric layer…” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the third dielectric layer…” will be construed to recite “…the at least one third dielectric layer…”, as in claim 1.
Claim 4 also recites the limitation “…the first conductive circuit…” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the first conductive circuit…” will be construed to recite “…the at least one first conductive circuit…”, as in claim 1.
Claim 5 recites the limitation “…the second dielectric layer…” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the second dielectric layer…” will be construed to recite “…the at least one second dielectric layer…”, as in claim 1.
Claim 5 also recites the limitation “…the second conductive circuit…” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the second conductive circuit…” will be construed to recite “…the at least one second conductive circuit…”, as in claim 1.
Claim 6 recites the limitation “…the fifth dielectric layer…” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the fifth dielectric layer…” will be construed to recite “…the at least one fifth dielectric layer…”, as in claim 4.
Claim 7 recites the limitation “…the fourth dielectric layer…” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the fourth dielectric layer…” will be construed to recite “…the at least one fourth dielectric layer…”, as in claim 5.
Claim 8 recites the limitation “…the conducting through hole…” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the conducting through hole…” will be construed to recite “…the at least one conducting through hole…”, as in claim 1.
Claim 11 recites the limitation “…the outside…” in line 15. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the outside…” will be construed to recite “…outside of the third surface and the fourth surface…”, as in claim 1.
Claim 11 also recites the limitation “…the substrate…” in lines 6 and 14. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the substrate…” will be construed to recite “…the at least one substrate…”.
Claim 11 also recites the limitation “…the fourth conductive circuit…” in line 11. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the fourth conductive circuit…” will be construed to recite “…the at least one fourth conductive circuit…”.
Claim 11 also recites the limitation “…the blind hole…” in line 6. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the blind hole…” will be construed to recite “…the at least one blind hole…”.
Claim 11 also recites the limitation “…the first conductive circuit…” in line 13. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the first conductive circuit…” will be construed to recite “…the at least one first conductive circuit…”.
Claim 11 also recites the limitation “…the second circuit layer…” in lines 15-16. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “…the second circuit layer…” will be construed to recite “…the at least one second circuit layer…”.
Allowable Subject Matter
Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 2-8 and 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 12-14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1: Anderson (US 20210183722 A1) shows some aspects of the chip package unit.
However, Anderson fails to disclose or suggest composed of at least one first dielectric layer, at least one bump, at least one third dielectric layer, at least one first conductive circuit, and at least one second lateral side arranged over the third surface in turn; wherein the at least one first dielectric layer is covering the third surface of the chip correspondingly and provided with a surface and at least one groove which is corresponding to the die pad of the chip; wherein the bump is disposed in the at least one groove of the at least one first dielectric layer and electrically connected with the die pad of the chip; wherein the at least one third dielectric layer is arranged at the surface of the at least one first dielectric layer and provided with a surface; wherein the at least one first conductive circuit is mounted to the surface of the at least one first dielectric layer, electrically connected with the at least one bump, and having an exposed surface; and a second redistribution layer (RDL) which is located at the fourth surface of the chip and composed of at least one second dielectric layer, at least one second conductive circuit, and at least one third lateral side arranged over the fourth surface in turn; wherein the at least one second dielectric layer is covering the fourth surface of the chip correspondingly and provided with a surface; wherein the at least one second conductive circuit is disposed on the surface of the at least one second dielectric layer and having an exposed surface; and at least one first circuit layer which is electrically connected with and disposed between the at least one first conductive circuit and the at least one second conductive circuit; the at least one first circuit layer is located at the at least one first lateral side of the chip, the at least one second lateral side of the first RDL, and the at least one third lateral side of the second RDL; wherein the chip is electrically connected outside of the third surface and the fourth surface by the at least one first conductive circuit or the at least one second conductive circuit; wherein the chip package unit is formed by cutting of a wafer separately and the chip is having a seventh surface and an eighth surface opposite to the seventh surface; wherein a plurality of the chip package units is arranged in an array and adjacent to one another on the wafer while a cut area is formed between the two adjacent chip package units and at least one conducting through hole is arranged at the cut area and axially penetrating the seventh surface and the eighth surface; the at least one conducting through hole is located at an outer edge of the at least one first lateral side of the chip, the at least one second lateral side of the first RDL, and the at least one third lateral side of the second RDL of the chip package unit; the at least one conducting through hole includes an axial connecting circuit therein and the axial connecting circuit is electrically connected with the at least one first conductive circuit and the at least one second conductive circuit of the chip package unit; wherein the cutting is performed by using cutting tools to cut the wafer along the cut area of the wafer; wherein a cut path with a width smaller than a width of the cut area is formed on the cut area of the wafer after the cutting; at the same time as formation of the cut path, a part of the at least one conducting through hole and a part of the axial connecting circuit are cut while a remaining part of the axial connecting circuit and a remaining part of the at least one conducting through hole are kept at an outer edge of the chip package unit to form the at least one first circuit layer of the chip package unit.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Kim (US 20230096170 A1) shows a chip package unit with a chip including at least one chip protection layer similar to that of the instant application.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
