DETAILED ACTION
Applicant’s amendment and response dated 9/4/2025 has been provided in response to the 6/5/2025 Office Action which rejected claims 1-20, wherein claims 3, 9, 13, 16, and 18 have been amended. Thus, claims 1-20 remain pending in this application and have been fully considered by the examiner.
Applicant's arguments have been fully considered but they are not persuasive. Accordingly, the rejection of the claims over the prior art in the previous office action is maintained and THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed 9/4/2025 have been fully considered but they are not persuasive.
In response to Applicant’s arguments regarding claim 1 (and similar independent claims 11 and 16) that “It is respectfully submitted claim 1 includes at least one limitation that is not disclosed or suggested by the references. Specifically, for example, claim 1 recites as follows:
A computer-implemented method to perform a firmware over the air (FOTA) process
at an autonomous driving vehicle (ADV), comprising:
determining a first firmware version at a complex programmable logic device (CPLD) executing the first firmware version; determining a second firmware version for the CPLD is available to the CPLD via a FOTA process;
performing a write operation to write data blocks corresponding to the second firmware version of the CPLD to a memory address of a data buffer of the CPLD;
instructing the CPLD to transfer the data blocks corresponding to the second firmware version from the data buffer to a configuration memory of the CPLD; and
causing the second firmware version at the configuration memory of the CPLD to load onto the CPLD.
(emphasis added).
It is respectfully submitted that Gandhi and Troia do not disclose the above emphasized claim limitations.
For example, although the Office Action acknowledges that Gandhi fails to disclose the features ‘instructing the CPLD to transfer the data blocks corresponding to the second firmware version from the data buffer to a configuration memory of the CPLD’, the Office Action contends that system memory 154 in paragraph 55 and 79 of Troia discloses these emphasized features. (Office Action, p. 5). Paragraph 55 and 79 of Troia, however, only discloses a system memory 154 being the memory of a system on a chip (SOC) device. Troia, Fig. 1; para. 42 (‘storage device 150, application controller 152, and system memory 154 are portions of a system-on-chip (SOC) device (e.g., all of these components are on the same SOC chip)’). Here, the SOC (or system 103, para. 74 of Troia) is not the same as a CPLD. The SOC integrates multiple components onto a single chip, whereas a CPLD is a type of programmable logic device that is used to implement custom digital logic functions. Furthermore, the memory 154 is a generic memory component used to store data, such as user data and configuration data associated with operation of the system 103. Troia, para. 75; 78 (‘The application controller 152 also controls loading of new data into the system memory 154’). Indeed, the system memory 154 of Troia, although may store configuration data, is used to support the SOC system 103. That is, Troia fails to disclose a CPLD and a configuration memory of the CPLD. In other words, Troia fails to disclose at least the features instructing the CPLD to transfer the data blocks corresponding to the second firmware version from the data buffer to a configuration memory of the CPLD.
Therefore, in view of above, Applicants respectfully submit that claim 1 is patentable over the cited references” (see Applicant’s remarks on pages 8-10), and also similar subsequent arguments (see pages 10-11 of Applicant’s remarks), the examiner respectfully disagrees.
The Gandhi and Troia references were used in combination to teach the limitations as claimed. In particular, Gandhi was cited to teach “a CPLD and a configuration memory of the CPLD (See. e.g. paragraphs [0031], [0077], [0082] and [0091]), Trois was cited to teach “transfer data blocks corresponding to the second firmware version from the data buffer to a configuration memory”(see e.g. paragraphs [0055] and [0079]), and the Applicant should please note that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As such, the combination of references teaches the limitations as claimed and the rejection of record is maintained.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 4, 10, 11, 14, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al. (US Patent Application Publication 2017/0249135 A1) in view of Troia et al. (US Patent Application Publication 2019/0391802 A1).
As to claim 1, Gandhi teaches a computer-implemented method to perform a firmware over the air (FOTA) process (see Figs. 1 and 7 and associated text, e.g. [0018]- initiating a local OTA update of firmware for the embedded system) comprising:
determining a first firmware version at a complex programmable logic device (CPLD) device executing the first firmware version (see e.g. [0031]- the status updates received from embedded system 150 can include the version number of a firmware component installed on embedded system 150 and [0078]- Host processing device 325 may alternatively or additionally include a programmable logic controller (PLC), a field programmable gate array (FPGA) or a complex programmable logic device (CPLD)),
determining a second firmware version for the CPLD is available to the CPLD via a FOTA process (see e.g. [0019], [0046]- remote control application 120 may receive information from WAN accessible service 130 that includes the newest firmware version number for the embedded system 150 and [0047]- Once the determination has been made that a LAN OTA firmware update for embedded system 150 is available, remote control application 120 may then receive an encrypted digital image containing the updated firmware from WAN accessible service 130),
causing the second firmware version at the configuration memory of the CPLD to load onto the CPLD (see e.g. [0077]- The embedded system 315 may include a host processing device 325, a host memory 330 and/or a communication module 350 coupled to the host processing device 325, [0082]- The processing device 355 may be a microcontroller, a system on a chip (SoC), a digital signal processor (DSP), a programmable logic controller (PLC), a microprocessor or programmable logic device such as a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD). The memory may include a non-volatile memory (e.g., RAM) and/or a volatile memory (e.g., ROM, Flash, etc.). In one embodiment, memory 365 is integrated into processing device 355, and [0091]- OTA update module 375 may retrieve the encrypted digital image from the location specified in the notification, and store it in memory 365 as firmware update 395; Subsequently, firmware update 395 may be installed to replace firmware 390).
Gandhi teaches instructing the CPLD (see e.g. [0031], [0079] and [0080]), but does not specifically teach an autonomous driving vehicle (ADV), performing a write operation to write data blocks corresponding to the second firmware version to a memory address of a data buffer, transfer the data blocks corresponding to the second firmware version from the data buffer to a configuration memory, or causing the second firmware version at the configuration memory to load.
In an analogous art of updating firmware, however, Troia teaches an autonomous driving vehicle (ADV) (see e.g. [0016]- a wireless transmission is used to update software (e.g., firmware) for one or more components of a vehicle. The vehicle can be, for example, an autonomous vehicle),
performing a write operation to write data blocks corresponding to a second firmware version (e.g. OTA update) to a memory address of a data buffer of a controller (see e.g. [0050]- an OTA update is received, via a wireless interface (not shown) of application controller 152 by buffer 204 as a stream of data portions (e.g., a data portion can be a page or a group of pages), transfer the data blocks corresponding to the second firmware version from the data buffer to a configuration memory(e.g. system memory 154, see e.g. [0055]- the data received by buffer 204 is code obtained from storage device 150. In response to determining to accept the data, application controller 152 copies the data from buffer 204 to system memory 154 and [0079]- System memory 154 can further include, for example, configuration data 112. Configuration data 112 can be, for example, data associated with operation of the system 103 as provided by the server 101. The configuration data 112 can be, for example, data that configures operation of the system 103, for example, based on conditions associated with the vehicle), and causing the second firmware version at the configuration memory to load (See e.g. [0096]- the firmware 104 can be initially stored in non-volatile storage media, such as by using system memory 154, or another non-volatile device (e.g., a storage device 150 and/or boot device 156), and loaded into the volatile DRAM 111 and/or the in-processor cache memory for execution by the controller 152).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and the teachings of Troia in order to provide a more efficient and secure method of updating software/firmware of vehicles components as needed.
As to claim 4, Troia further teaches receiving, from a firmware over the air (FOTA) server, data corresponding to the second firmware version (see e.g. [0067]- application controller 152 receives an update from a remote location; application controller 152 stores the received update inside system memory 154 and/or stores the signature of the update inside system memory 154) and determining an integrity of the received data, including determining a checksum of the received data and comparing the determined checksum and an expected checksum of the received data (see e.g. [0069]- when an update is downloaded by application controller 152, an image is stored first in system memory (e.g., DRAM), and/or from time-to-time stored in storage device 150. The update is signed (by calculating its MAC) and the signature is the mechanism to ensure that the downloaded content inside the memory is authentic. To perform a check of the signature, all of the data is downloaded, the data is measured against the internal application secret key, and then the final signature is compared with the received signature and [0070]- the cryptographic measurement is a digest determined using a MAC algorithm. The measure of the OTA update implements the MAC, for example, based on a secret key (e.g., HMAC-SHA256), which is known between the system (e.g., boot device) and the authority (e.g., server or other computing device or source) sending the update).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and the teachings of Troia in order to provide a more efficient and secure method of updating software/firmware of vehicles components as needed.
As to claim 10, Gandhi also teaches retrieving a status of the FOTA process indicating whether the FOTA process completed successfully (see e.g. [0065]- OTA update manager 215 may then receive a status from the embedded system that indicates whether the encrypted digital image was successfully retrieved and installed. OTA update manager 215 may then forward the status to the WAN accessible service).
As to claim 11, the limitations of claim 11 are substantially similar to the limitations of claim 1, and therefore, it is rejected for the reasons stated above.
As to claim 14, the limitations claim 14 are substantially similar to the limitations of device claim 4, and therefore, it is rejected for the reasons stated above.
As to claim 16, the limitations of claim 16 are substantially similar to the limitations of claim 1, and therefore, it is rejected for the reasons stated above.
As to claim 19, the limitations claim 19 are substantially similar to the limitations of device claim 4, and therefore, it is rejected for the reasons stated above.
6. Claims 5, 15, and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al. (US Patent Application Publication 2017/0249135 A1) in view of Troia et al. (US Patent Application Publication 2019/0391802 A1), as applied to claims 1, 11, and 16 above, and further in view of Lambert et al. (US Patent 10,585,816 B1).
As to claim 5, Gandhi teaches the CPLD (see [0031]), but does not specifically teach wherein the data blocks are transferred from the data buffer to the configuration memory.
In an analogous art of updating firmware, however Troia teaches wherein the data blocks are transferred from the data buffer to the configuration memory (see e.g. [0050]- an OTA update is received, via a wireless interface (not shown) of application controller 152 by buffer 204).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and the teachings of Troia in order to provide a more efficient and secure method of updating software/firmware of vehicles components as needed.
Gandhi in view of Troia does not specifically teach in a burst mode.
In an analogous art of updating firmware, however, Lambert teaches a burst mode (see Fig.6 and associated txt e.g. col.7 lines 28-30 and lines 37-39: FIG. 6 illustrates transmission of a sequence of payloads by peripheral interface device 195 to CPLD 190 via SWI 192; payloads transmitted by peripheral interface device 195 during state S5 can be sent in their entirety in a single burst).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and the teachings of Troia in order to provide a more efficient method of transferring software/firmware of devices as needed.
As to claim 15, the limitations of claim 15 are substantially similar to the limitations of claim 5, and therefore, it is rejected for the reasons stated above.
As to claim 20, the limitations of claim 20 are substantially similar to the limitations of claim 5, and therefore, it is rejected for the reasons stated above.
7. Claims 2, 3, 6, 9, 12, 13, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al. (US Patent Application Publication 2017/0249135 A1) in view of Troia et al. (US Patent Application Publication 2019/0391802 A1), as applied to claims 1, 11, and 16 above, and further in view of Seater et al. (US Patent Application Publication 2020/0257517 A1).
As to claim 2, Gandhi in view of Troia teaches wherein the second firmware version of the CPLD configures the CPLD (see Gandhi [0031] and [0109]) and an autonomous driving vehicle (see Troia: [0016]), but does not specifically teach to perform a power on or a power reset operation for a peripheral component interconnect express (PCIe) device, or perform a power on or power reset operation for one or more sensors.
In an analogous art of updating firmware, however Seater teaches a CPLD can perform a power on or a power reset operation for a peripheral component interconnect express (PCIe) device [or perform a power on or power reset operation for one or more sensors of the autonomous driving vehicle] (see e.g. [0017]- CPLD 208 can control power reset to merely device 202 that is subject to a seamless firmware update or upgrade without causing power disruption to another device that is not subject to a firmware update when merely device 202 receives a firmware update and [0028] Host connector 210 can be an interface for at least device 202 and CPLD 208 to host device 250. For example, device 202 can be connected as a PCIe device with host device 250. Host connector 210 can be a PCIe compatible connector, SMBus, or other interface).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and Troia to the teachings of Seater in order to provide a more efficient method of updating software/firmware of devices for the purpose of minimizing downtime.
As to claim 3, Seater further teaches reading a memory address of a register file, retrieving a value of the register file based on the memory address of the register file, and determining a memory address of the configuration memory based on the value of the register file (See e.g. [0012] and [0029]- NUT 252 identifies parameters of device 202 (e.g., base address register (BAR) and configuration space 203 (e.g., PF configurations)) of device 202 and saves it into memory of host device 250; At (7), NUT 252 restores the saved configuration to device 202 to configuration space 203. Thereafter, device 202 can use the updated firmware).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and Troia to the teachings of Seater in order to provide a more efficient method of updating software/firmware of devices for the purpose of minimizing downtime.
As to claim 6, Seater further teaches wherein read and write operations are performed by a host system onto the CPLD through a microcontroller, wherein the microcontroller is configured to forward communication packets between the host system and the CPLD (see Fig.2 and associated text, e.g. [0028]- Host connector 210 can be an interface for at least device 202 and CPLD 208 to host device 250. For example, device 202 can be connected as a PCIe device with host device 250. Host connector 210 can be a PCIe compatible connector, SMBus, or other interface, [0029]- NUT 252 identifies parameters of device 202 (e.g., base address register (BAR) and configuration space 203 (e.g., PF configurations)) of device 202 and saves it into memory of host device 250. At (2) NUT 252 notifies CPLD 208 of a firmware update operation via a sideband signal (e.g., SMBUS) and [0035]- Processor 510 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware to provide processing for system 500, or a combination of processors).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and Troia to the teachings of Seater in order to provide a more efficient method of updating software/firmware of devices for the purpose of minimizing downtime.
As to claim 9, Gandhi in view of Troia teaches the CPLD and to update a firmware version for the CPLD (see Gandhi: e.g. [0031], [0077], [0082], and [0091]), but does not specifically teach wherein the CPLD is configured to a reconfiguration on the fly mode for the FOTA process.
In an analogous art of updating firmware, however, Seater teaches wherein the CPLD is configured to a reconfiguration on the fly mode for the FOTA process (e.g. without causing disruption in operation, see e.g. [0025]- CPLD 208 can turn on or off power merely to device 202 to cause loading of a firmware update for device 202 but not cause a power disruption or reset of any other device that is not having a firmware update or change).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and Troia to the teachings of Seater in order to provide a more efficient method of updating software/firmware of devices for the purpose of minimizing downtime.
As to claim 12, the limitations of claim 12 are substantially similar to the limitations of claim 2, and therefore, it is rejected for the reasons stated above.
As to claim 13, the limitations claim 13 are substantially similar to the limitations of device claim 3, and therefore, it is rejected for the reasons stated above.
As to claim 17, the limitations of claim 17 are substantially similar to the limitations of claim 2, and therefore, it is rejected for the reasons stated above.
As to claim 18, the limitations of claim 18 are substantially similar to the limitations of claim 3, and therefore, it is rejected for the reasons stated above.
8. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al. (US Patent Application Publication 2017/0249135 A1) in view of Troia et al. (US Patent Application Publication 2019/0391802 A1) and Seater et al. (US Patent Application Publication 2020/0257517 A1), as applied to claim 6 above, and further in view of Nolan et al. (US Patent Application Publication 2019/0042228 A1).
As to claim 7, Gandhi in view of Troia and Seater teaches the read and write operations (see Seater: [0028] and [0029]), but does not specifically teach according to an I2C protocol.
In an analogous art of updating firmware, however, Nolan teaches performing operations according to an I2C protocol (see e.g. [0022]- The connector 126 provides an interface or communication channel between the replacement part 100, via its resource interface 112, and the target device 130, e.g., the IoT/fog device. In some embodiments, the connector 126 provides an I2C serial bus connection. I2C is a 2-wire serial bus, connecting low-speed devices, such as microcontrollers, in embedded systems).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi, Troia, and Seater to the teachings of Nolan in order to provide a more efficient method of updating software/firmware of devices for the purpose of increasing performance.
9. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Gandhi et al. (US Patent Application Publication 2017/0249135 A1) in view of Troia et al. (US Patent Application Publication 2019/0391802 A1), as applied to claim 1 above, and further in view of Nolan et al. (US Patent Application Publication 2019/0042228 A1)..
As to claim 8, Gandhi in view of Troia teaches wherein a host system communicates with a microcontroller via ethernet communication (see Gandhi: [0023] and [0078]) and the CPLD (see Gandhi: [0031]), but does not specifically teach the microcontroller communicates through an I2C interface.
In an analogous art of updating firmware, however, Nolan teaches teach a microcontroller communicates through an I2C interface (see e.g. [0020]- the replacement part 100 includes a microcontroller unit (MCU) 102 and [0022]- The connector 126 provides an interface or communication channel between the replacement part 100, via its resource interface 112, and the target device 130, e.g., the IoT/fog device. In some embodiments, the connector 126 provides an I2C serial bus connection. I2C is a 2-wire serial bus, connecting low-speed devices, such as microcontrollers, in embedded systems).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gandhi and Troia to the teachings of Nolan in order to provide a more efficient method of updating software/firmware of devices for the purpose of increasing performance.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHENECA SMITH whose telephone number is (571)270-1651. The examiner can normally be reached Mon-Fri 8:00AM-4:30PM EST.
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/CHENECA SMITH/Examiner, Art Unit 2192
/S. Sough/SPE, Art Unit 2192