DETAILED ACTION
The instant action is in response to application 12 December 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The specification objections have been withdrawn.
There were no remarks with respect to priority. It will be assumed applicant’s present date is valid, but applicant is advised that the date must be clearly filed before a patent can issue.
The record has been made sufficiently clear with respect to claims 5 and 7, and claim 9 appears to be in proper form. The 112(b) rejections have been withdrawn.
Applicant’s response on the merit have been considered but are moot for not considering the present references.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on October 2022. It is noted, however, that a certified copy has not been received.
It is noted that applicant tried to have the office electronically retrieve a copy of the foreign priority, though the attempt was not successful as detailed in the letter mailed in March of 2024.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 9, 10 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Bernardon (US 20030214276 ).
As to claim 1, Bernardon (see annotated image below) teaches a switch circuit (ptype transistor 1, unlabeled n type transistor in series) configured to generate an output voltage (Vout) by switching an input voltage (unlabelled battery source) and a ground voltage based (GND) on a driving control signal (output 2); an error voltage generator configured to generate an error voltage based on a comparison between the output voltage (Vout) and a reference voltage (Desired Reference Voltage); a duty signal generator configured to generate a duty signal, and to select one from among a constant pulse frequency and a modulated pulse frequency (abstract “controlling the switching device with the first control circuit functioning in a pulse width modulation mode and in an alternative manner with a second control circuit functioning in a pulse frequency modulation mode”), based on a result of the comparing (when item 4 determines its 60mV below the reference,it goes into a PWM mode from a PFM mode); and a driving controller configured to generate the driving control signal based on the duty signal.
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As to claim 2, Bernardon teaches wherein based on the error voltage being greater than the reference voltage, the duty signal generator is further configured to generate the duty signal having the constant pulse frequency, and to change a duty cycle of the duty signal (this occurs when PWM mode occurs. PWM control has constant frequency and varies the duty according to the error signal).
As to claim 3, Bernandon teaches wherein based on the error voltage being less than or equal to the reference voltage, the duty signal generator is further configured to generate the duty signal having the modulated pulse frequency, and to change a duty cycle of the duty signal (when sufficiently undervoltage, the system switches to PWM mode).
As to claim 9, Bernandon teaches wherein the driving control signal comprises a first driving control signal (signal fed to HS power FET) and a second driving control signal (signal fed to LS power FET) ; and wherein the switch circuit comprises: a first driving (1) element connected between a first node (10) configured to receive the input voltage and a switching node (SW), and comprising a control terminal configured to receive the first driving control signal; a second driving (ntype transistor) element connected between the ground voltage and the switching node, and comprising a control terminal configured to receive the second driving control signal; and an inductor (5) connected between the switching node and the second node.
As to claim 10, Michishita teaches wherein based on the duty signal and the driving control signal transitioning to a logic high level, the driving controller is further configured to output the first driving control signal having the logic high level and to output the second driving control signal having a logic low level, and wherein based on the duty signal and the driving control signal transitioning to the logic low level, the driving controller is further configured to output the first driving control signal having the logic low level and to output the second driving control signal having the logic high level (this is how a buck converter works).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bernardon (US 20030214276 ) in view of Michishita (US 20090322299) and Dearborn (US 20110006744).
As to claim 4, Bernardon teaches an RS flipflop and comparator. He does not explicitly teach wherein the duty signal generator comprises: an oscillator configured to generate an oscillating signal having a period which is based on a difference between the error voltage and the reference voltage; a ramp signal generator configured to generate a ramp signal having a slope which is based on a value of the error voltage; a first hysteresis comparator configured to compare the error voltage and the ramp signal to output a reset signal; and an R/S flip-flop comprising a first input terminal configured to receive the oscillating signal, a second input terminal configured to receive the reset signal, and an output terminal configured to output the duty signal having a logic high level at an edge of the oscillating signal, and to output the duty signal having a logic low level at an edge of the reset signal.
Michishita teaches wherein the duty signal generator comprises: an oscillator configured to generate an oscillating signal having a period which is based on a difference between the error voltage and the reference voltage (Ve fed into oscillator); a ramp signal generator configured to generate a ramp signal (4) having a slope which is based on a value of the error voltage; a first
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the PWM circuit of Mishita to have a redundant PFM/PWM control scheme should a comparator fail.
The combination not specifically disclose first hysteresis comparator configured to compare the error voltage and the ramp signal.
A hysteresis comparator is an obvious variation of a comparator performing a similar function. As such, it is an obvious variation. Dearborn teaches first hysteresis comparator configured to compare the error voltage and the ramp signal (310).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to add the hysteresis comparator to provide PFM mode.
Claim 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Bernardon (US 20030214276 ) in view of Ramsey (US 6215288).
As to claim 11, MIshita discloses a current sensor (7). He does not disclose further comprising a current sensor configured to output a sensing signal representing a zero- current level of a current flowing in the inductor, wherein the driving controller is further configured to change the second driving control signal to a logic low level based on the sensing signal.
Ramsey teaches further comprising a current sensor configured to output a sensing signal representing a zero- current level of a current flowing in the inductor, wherein the driving controller is further configured to change the second driving control signal to a logic low level based on the sensing signal (Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of above to use reverse current flow as described in Ramsey to prevent unnecessary capacitor discharge.
As to claim 12, Bernardon in view of Ramsey teaches wherein a ramp signal has an initial voltage level corresponding to an amount of the current flowing through the inductor (7).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bernardon (US 20030214276 ) in view of Sareen (US 20230133452).
As to claim 20, Bernardon teaches A power system comprising:a switch circuit comprising: a first driving element configured to connect a first node and a switching node based on a first driving control signal, a second driving element configured to connect a ground voltage and the switching node based on a second driving control signal, and an inductor connected between the switching node and a second node; and a charging controller configured to: generate an error voltage based on a smaller of a difference between the voltage of the first node and a first reference voltage, and a difference between a voltage of the switching node and a second reference voltage (see above),
He does not explicitly teach decrease a period of the first driving control signal and a period of the second driving control signal based on the error voltage increasing.
Sareen teaches decrease a period of the first driving control signal and a period of the second driving control signal based on the error voltage increasing (Fig. 2, 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of above to use pulse skipping as described in Sareen to increase the functional frequency range of the oscillator.
Allowable Subject Matter
Claims 5-8 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5, the prior art fails to disclose: “wherein the oscillator comprises: a current source connected between a power voltage and a node and configured to generate a first current; a dependent current source connected between the node and the ground voltage and configured to generate a second current based on the difference between the error voltage and the reference voltage; a capacitor connected between the node and the ground voltage; and a second hysteresis comparator comprising a first input terminal connected to the node, a second input terminal configured to receive an oscillating reference voltage, and an output terminal configured to output the oscillating signal.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 7, the prior art fails to disclose " wherein the ramp signal generator comprises: a current source connected between a power voltage and a first node and configured to generate a first current; a dependent current source connected between the first node and the ground voltage and configured to generate a second current based on the difference between the error voltage and the reference voltage; a capacitor connected between the first node and a second node; and a resistor connected between the second node and the ground voltage.” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sean Kayes can be reached on 571-272-8931. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/Primary Examiner, Art Unit 2839
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