DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/08/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 6, 9, 13, 16, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patel et al (hereinafter Patel), US 20190050263 A1.
Referring to claims 1, 9, and 16, taking claim 1 as exemplary, Patel discloses an accelerator device, comprising:
a plurality of hardware accelerators [paragraph 10, “The compute device 110 is equipped with a pool of accelerator devices 160”]; and
circuitry configured to execute one or more instructions to cause the circuitry to:
receive, from an application, an application programming interface (API) call to chain an encryption operation for data and a data transformation operation for the data [paragraphs 10, 24, 26, “one or more of the applications 140 may request (e.g., through an application programming interface (API) call to an operating system executed by the compute device 110) acceleration of one or more operations (e.g., functions) of the corresponding application 140”; “the type of each function (e.g., encryption, compression, convolution, etc.) may be included as a parameter of the request”; “accelerate multiple functions associated with a sequence (e.g., encryption followed by compression of a data set)”; (where encryption is equivalent to the claimed encryption operation and compression is equivalent to the claimed data transformation operation)]; and
cause two or more of the hardware accelerators to execute the encryption operation for the data and the data transformation operation for the data based on the API call [paragraphs 10, 24, 26, one or more of the applications 140 may request (e.g., through an application programming interface (API) call to an operating system executed by the compute device 110) acceleration of one or more operations (e.g., functions) of the corresponding application 140; The compute device 110 is equipped with a pool of accelerator devices 160 capable of executing operations faster than a general purpose processor. The compute device 110 additionally includes an acceleration scheduler logic unit 150, capable of assigning (e.g., scheduling) the acceleration of functions among the accelerator devices 160; the compute device 110 schedules the requested acceleration using the acceleration scheduler logic unit 150…determines parameters of the request for acceleration…The type of each function (e.g., encryption, compression, convolution, etc.) may be included as a parameter of the request; “accelerate multiple functions associated with a sequence (e.g., encryption followed by compression of a data set)”; As indicated in block 362, the acceleration scheduler logic unit 150 may also determine a time estimate to transfer output data (e.g., data produced by the accelerator device 160 in performing the requested function on the input data set) to another accelerator device; “compute device 110 executes the scheduled functions with the accelerator devices 160”].
Referring to claims 2, 10, and 17, taking claim 2 as exemplary, Patel discloses the accelerator device of claim 1, the circuitry configured to execute one or more instructions to cause the circuitry to:
determine an order of execution for the encryption operation and the data transformation operation [paragraphs 10, 24, 26, The compute device 110 additionally includes an acceleration scheduler logic unit 150, capable of assigning (e.g., scheduling) the acceleration of functions among the accelerator devices 160; “accelerate multiple functions associated with a sequence (e.g., encryption followed by compression of a data set)”; where scheduling determines an order of execution];
cause the two or more of the hardware accelerators to execute the encryption operation and the data transformation operation according to the determined order [paragraphs 10, 24, 26, As indicated in block 362, the acceleration scheduler logic unit 150 may also determine a time estimate to transfer output data (e.g., data produced by the accelerator device 160 in performing the requested function on the input data set) to another accelerator device; “compute device 110 executes the scheduled functions with the accelerator devices 160”].
Referring to claims 5, 13, and 20, taking claim 5 as exemplary, Patel discloses the accelerator device of claim 1, the circuitry configured to execute one or more instructions to cause the circuitry to, prior to the receipt of the API call:
establish a session with the application [fig. 4, steps 334, 338]; and
receive, from the application, one or more parameters for the session [paragraphs 10, 24, 26, the compute device 110 schedules the requested acceleration using the acceleration scheduler logic unit 150…determines parameters of the request for acceleration…The type of each function (e.g., encryption, compression, convolution, etc.) may be included as a parameter of the request].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 7, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patel et al (hereinafter Patel), US 20190050263 A1, in view of Agarwal et al (hereinafter Agarwal), US 20180189104 A1.
Referring to claims 3, 11, and 18, taking claim 3 as exemplary, Patel discloses the accelerator device of claim 1, wherein the data transformation operation is to comprise a compression operation, wherein the two or more of the hardware accelerators are to comprise an encryption accelerator and a compression accelerator [paragraph 10, 24, 26, “The compute device 110 is equipped with a pool of accelerator devices 160 which each may be embodied as any device or circuitry (e.g., a field programmable gate array (FPGA), a co-processor, a graphics processing unit (GPU), etc.) capable of executing operations faster than a general purpose processor”; “accelerate multiple functions associated with a sequence (e.g., encryption followed by compression of a data set)”], the circuitry configured to execute one or more instructions to cause the circuitry to:
cause the compression accelerator to compress the data to produce compressed data [paragraphs 10, 24, 26, one or more of the applications 140 may request (e.g., through an application programming interface (API) call to an operating system executed by the compute device 110) acceleration of one or more operations (e.g., functions) of the corresponding application 140; The compute device 110 is equipped with a pool of accelerator devices 160 capable of executing operations faster than a general purpose processor. The compute device 110 additionally includes an acceleration scheduler logic unit 150, capable of assigning (e.g., scheduling) the acceleration of functions among the accelerator devices 160; the compute device 110 schedules the requested acceleration using the acceleration scheduler logic unit 150…determines parameters of the request for acceleration…The type of each function (e.g., encryption, compression, convolution, etc.) may be included as a parameter of the request; “accelerate multiple functions associated with a sequence (e.g., encryption followed by compression of a data set)”; As indicated in block 362, the acceleration scheduler logic unit 150 may also determine a time estimate to transfer output data (e.g., data produced by the accelerator device 160 in performing the requested function on the input data set) to another accelerator device; “compute device 110 executes the scheduled functions with the accelerator devices 160”].
Patel does not explicitly disclose cause the encryption accelerator to encrypt the compressed data to produce encrypted compressed data.
However, Agarwal discloses cause the encryption accelerator to encrypt the compressed data to produce encrypted compressed data [paragraph 34, “a host software chaining offload requests across accelerators, where an accelerator device may forward work to another host software specified accelerator to chain work without bouncing through host (e.g., a compression accelerator compressing first, before chaining work to a bulk-crypto accelerator for encryption on the compressed data)”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Agarwal in the device of Patel to implement, cause the encryption accelerator to encrypt the compressed data to produce encrypted compressed data, for efficient inline acceleration [Agarwal, paragraph 34].
Referring to claim 7, Patel does not explicitly disclose the accelerator device of claim 5, the circuitry configured to execute one or more instructions to cause the circuitry to:
receive, from the application, another API call to chain the encryption operation and data transformation operation for another data; and
cause two or more of the hardware accelerators to execute the encryption operation for the another data and the data transformation operation for the another data based at least in part on the one or more parameters for the session.
However, Patel discloses receive, from the application, a first API call to chain the encryption operation and data transformation operation for a first data [paragraphs 10, 24, 26, “one or more of the applications 140 may request (e.g., through an application programming interface (API) call to an operating system executed by the compute device 110) acceleration of one or more operations (e.g., functions) of the corresponding application 140”; “the type of each function (e.g., encryption, compression, convolution, etc.) may be included as a parameter of the request”; “accelerate multiple functions associated with a sequence (e.g., encryption followed by compression of a data set)”]; and
cause two or more of the hardware accelerators to execute the encryption operation for the first data and the data transformation operation for the first data based at least in part on the one or more parameters for the session [paragraphs 10, 24, 26, one or more of the applications 140 may request (e.g., through an application programming interface (API) call to an operating system executed by the compute device 110) acceleration of one or more operations (e.g., functions) of the corresponding application 140; The compute device 110 is equipped with a pool of accelerator devices 160 capable of executing operations faster than a general purpose processor. The compute device 110 additionally includes an acceleration scheduler logic unit 150, capable of assigning (e.g., scheduling) the acceleration of functions among the accelerator devices 160; the compute device 110 schedules the requested acceleration using the acceleration scheduler logic unit 150…determines parameters of the request for acceleration…The type of each function (e.g., encryption, compression, convolution, etc.) may be included as a parameter of the request; “accelerate multiple functions associated with a sequence (e.g., encryption followed by compression of a data set)”; As indicated in block 362, the acceleration scheduler logic unit 150 may also determine a time estimate to transfer output data (e.g., data produced by the accelerator device 160 in performing the requested function on the input data set) to another accelerator device; “compute device 110 executes the scheduled functions with the accelerator devices 160”].
It has been held that duplication of parts is an obvious variant [MPEP, 2144.04, VI., B., In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.) The examiner notes that performing “another” API call to operate on “another” data is an obvious variant and merely repeats claim 1 for “another” data, which is a duplication of already known steps.
Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patel, in view of Neiger et al (hereinafter Neiger), US 20160179721 A1.
Referring to claims 8 and 15, taking claim 8 as exemplary, Patel does not explicitly disclose the accelerator device of claim 1, the circuitry configured to execute one or more instructions to cause the circuitry to:
return, to the application, a callback to indicate completion of the encryption operation and the data transformation operation.
However, Neiger discloses return, to the application, a callback to indicate completion of the encryption operation and the data transformation operation [paragraph 17, “When the I/O device completes the operation, it may notify the application via an interrupt, which may be handled by the OS kernel and the device driver. The latter may then notify the application (e.g., by invoking a callback handler that was previously registered by the application)”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Neiger in the device of Patel to implement, return, to the application, a callback to indicate completion of the encryption operation and the data transformation operation, in order to reduce or eliminate software latencies to improve operational aspects of various user-level applications interacting with I/O devices [Neiger, paragraph 18].
Allowable Subject Matter
Claims 4, 6, 14, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the data transformation operation is to comprise a compression operation and a hash operation, wherein the circuitry is configured to cause the two or more of the hardware accelerators to execute the compression operation and the hash operation in parallel, in combination with other recited limitations in claim 4.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest the one or more parameters to comprise an encryption algorithm for the data and a parameter for the data transformation operation, in combination with other recited limitations in claim 6.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest the one or more parameters to comprise an encryption algorithm for the data and a parameter for the data transformation operation in combination with other recited limitations in claim 14.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the data transformation operation is to comprise a compression operation and a hash operation, wherein the accelerator device is configured to cause the two or more hardware accelerators to execute the compression operation and the hash operation in parallel, in combination with other recited limitations in claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Zhou et al, US 20240037104 A1, discloses when the hierarchy accelerator module is enabled and the encrypted and/or compressed database data is loaded from the storage media on the host side, the decompression and/or decryption of the data needs to be completed by the master accelerator card first, and then distributed to each the accelerator card (including the master and the slave accelerator cards). When the result data needs to be persisted on disk, each the slave accelerator card aggregates the execution results to the master accelerator card, and then the master accelerator card completes encryption and/or compression and sends them to the host side for persistent storage [paragraph 81].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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