DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-10 and 20, in the reply filed on 06/23/2026 is acknowledged.
Claims 11-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/23/2026.
Claim Objections
Claim 6 is objected to because of the following informalities: “the electrical connection configured to electrically connect the first through silicon via of the cap wafer of the bottom filter and the first through silicon via device wafer of the bottom filter” (emphasis added), should instead disclose: “the electrical connection configured to electrically connect the first through silicon via of the cap wafer of the bottom filter and the first through silicon via of the device wafer of the bottom filter”. This is because it is not a “through silicon via device wafer”, but is instead a “via of the device wafer”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dogiamis et al. (US 2021/0175873 A1).
Regarding claim 1, Dogiamis discloses a multi-layer piezoelectric substrate silicon package (100) comprising a bottom filter (105, 110, 197) including a cap wafer (105) of the bottom filter, and a device wafer (120 and/or 125) of the bottom filter (fig. 1; pars. 0029-0031), the cap wafer of the bottom filter and the device wafer of the bottom filter each having a first *through silicon via (150, 155 and 190) configured to provide an electrical path from a first bottom terminal (right one of 135) of the device wafer of the bottom filter to a first top terminal (185b) of the cap wafer of the bottom filter (fig. 1; pars. 0032-0035).
*NOTE: the wafers are not explicitly disclosed as being formed of silicon, and there is no explicit disclosure in the specification of this either. The use of the term “through silicon via” in the claim implies that the wafers may be silicon, but it is not required as presented. In the same manner, there is nothing in claim 1 which actually requires any piezoelectric material. The term “filter” is often used to refer to a structure including a piezoelectric element, however there are numerous other “filters” which do not require any piezoelectric material whatsoever. As such, the language directed to a piezoelectric in the preamble is not currently held to breathe life or meaning into any of the claims. Additionally, the disclosure of “a first through silicon via configured to provide an electrical path” is broad, and is understood to intend a typical industry standard “through silicon via” (TSV), which can contain a conductive material in order to facilitate the via being “configured to provide an electrical path”. That being so, the TSV of claim 1 does not currently require a conductor or any electrical connection. This interpretation is verified by the fact that claim 6 is the first instance of a positively recited electrical connection.
Regarding claim 2, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 1 wherein the bottom filter comprises one of a surface acoustic wave (SAW) device of the bottom filter or a bulk acoustic wave (BAW) device of the bottom filter arranged between the cap wafer of the bottom filter and the device wafer of the bottom filter (acoustic wave resonator: par. 0001).
Regarding claim 3, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 2 wherein the device wafer of the bottom filter comprises a second through silicon via (165) configured to provide an electrical path from a second bottom terminal (middle one of 135) of the device wafer of the bottom filter to the SAW device of the bottom filter or the BAW device of the bottom filter (fig. 1; pars. 0030 and 0033).
Regarding claim 4, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 2 wherein the bottom filter comprises a seal ring (185) arranged between the cap wafer of the bottom filter and the device wafer of the bottom filter (pars. 0028 and 0038).
Regarding claim 5, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 2 wherein the bottom filter comprises a support pillar (175) arranged between the cap wafer of the bottom filter and the device wafer of the bottom filter.
Regarding claim 6, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 2 wherein the bottom filter comprises an electrical connection arranged between the cap wafer of the bottom filter and the device wafer of the bottom filter, the electrical connection configured to electrically connect the first through silicon via of the cap wafer of the bottom filter and the first through silicon via device wafer of the bottom filter (fig. 1; pars. 0030-0035).
Regarding claim 20, Dogiamis discloses a mobile device (1800) comprising a multiplexer (multi-filter AWR) (figs. 1 and 10; pars. 0087 and 0093-0098); including a multi-layer piezoelectric substrate silicon package (100) having a bottom filter (105, 110, 197) having a cap wafer (105) of the bottom filter (fig. 1; pars. 0029-0031), and a device wafer (120 and/or 125) of the bottom filter, the cap wafer of the bottom filter and the device wafer of the bottom filter each having a first through silicon via (150, 155 and 190) configured to provide an electrical path from a first bottom terminal (right one of 135) of the device wafer of the bottom filter to a first top terminal (185b) of the cap wafer of the bottom filter (fig. 1; pars. 0032-0035).
Claims 1-2 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dogiamis et al. (WO 2019/132921 A1; hereinafter referred to as Dogiamis-2).
Regarding claim 1, Dogiamis-2 discloses a multi-layer piezoelectric substrate silicon package (figs. 1 and 6A: all) comprising a bottom filter (6501) including a cap wafer (124) of the bottom filter, and a device wafer (122) of the bottom filter (fig. 1; pg. 4, lines 17-26), the cap wafer of the bottom filter and the device wafer of the bottom filter each having a first *through silicon via (filled with 155 and 171/172) configured to provide an electrical path from a first bottom terminal (215) of the device wafer of the bottom filter to a first top terminal (one of 157) of the cap wafer of the bottom filter (fig. 1-2 and 6A; pg. 5, lines 4-15; pg. 6, lines 19-24 and lines 29-35).
*NOTE: Please refer to “NOTE”, above, applied to claim 1.
Regarding claim 2, Dogiamis-2 discloses the multi-layer piezoelectric substrate silicon package of claim 1 wherein the bottom filter comprises one of a surface acoustic wave (SAW) device of the bottom filter or a bulk acoustic wave (BAW) device of the bottom filter arranged between the cap wafer of the bottom filter and the device wafer of the bottom filter (pg. 3, lines 13-23).
Regarding claim 7, Dogiamis-2 discloses the multi-layer piezoelectric substrate silicon package of claim 1 further comprising a top filter (6502) including a cap wafer (top one of 124) of the top filter, and a device wafer (121 and/or bottom one of 124) of the top filter, the device wafer of the top filter having a first through silicon via of the top filter and a bottom terminal of the device wafer of the top filter configured to provide an electrical path from the first top terminal of the cap wafer of the bottom filter or a first top terminal of the cap wafer of an intermediate filter to a SAW device of the top filter or a BAW device of the top filter arranged between the cap wafer of the top filter and the device wafer of the top filter (figs. 1, 2, 4 and 6; pg. 9, lines 2-12).
Regarding claim 8, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 7 wherein the top filter further comprises a seal ring (110) arranged between the cap wafer of the top filter and the device wafer of the top filter.
Regarding claim 9, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 7 wherein the top filter further comprises a support pillar (110) arranged between the cap wafer of the top filter and the device wafer of the top filter.
Regarding claim 10, Dogiamis discloses the multi-layer piezoelectric substrate silicon package of claim 1 further comprising an intermediate filter (6502) including a cap wafer (top one of 124) of the intermediate filter, and a device wafer (121 and/or bottom one of 124) of the intermediate filter, the cap wafer of the intermediate filter and the device wafer of the intermediate filter each having a first through silicon via configured to provide an electrical path from a first bottom terminal of the device wafer of the intermediate filter to a first top terminal of the cap wafer of the intermediate filter (figs. 1, 2, 4 and 6; pg. 9, lines 2-12).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the concurrently mailed PTO-892, as all of those cited references are considered to be pertinent to the claimed invention. For example, Takayama et al. (US 2009/0051245 A1) is held to disclose most if not all of the limitations of at least claim 1. Takayama discloses a multi-layer piezoelectric substrate silicon package (10B) comprising a bottom filter (11, 11A, 14, 15) including a cap wafer (15) of the bottom filter, and a device wafer (14) of the bottom filter (fig. 3; pars. 0017-0019), the cap wafer of the bottom filter and the device wafer of the bottom filter each having a first through silicon via (filled by 16) configured to provide an electrical path from a first bottom terminal (13) of the device wafer of the bottom filter to a first top terminal (17) of the cap wafer of the bottom filter (fig. 3; pars. 0017-0019, 0021-0023 and 0026). The Takayama reference is not currently applied as an anticipation rejection due to the completeness of the above applied art, and in order to avoid an overly long Office Action or duplicative rejections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey T Carley whose telephone number is (571)270-5609. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
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