Prosecution Insights
Last updated: August 18, 2026
Application No. 18/221,136

SYSTEMS AND METHODS FOR EXECUTING FIRMWARE UPGRADES

Non-Final OA §102
Filed
Jul 12, 2023
Priority
Sep 10, 2021 — CIP of PCTCN2021117732
Examiner
KENDALL, CHUCK O
Art Unit
2192
Tech Center
2100 — Computer Architecture & Software
Assignee
Schneider Electric SE
OA Round
3 (Non-Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
805 granted / 927 resolved
+31.8% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
23 currently pending
Career history
948
Total Applications
across all art units

Statute-Specific Performance

§101
12.9%
-27.1% vs TC avg
§103
22.2%
-17.8% vs TC avg
§102
50.4%
+10.4% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 927 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is in response to Application filed 06/02/26. Claims 1 – 9, 11 – 16, 18 – 22 and 24 has been amended. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 – 9, 11 – 16, 18 – 22 and 24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by AMUNDSEN et al. US 20220342657 A1. Regarding claims 1, 12 and 18, AMUNDSEN anticipates a bootloader system/method/ non-transitory computer-readable media comprising: a volatile memory [0044. See volatile memory]; a first non-volatile memory configured to store a first bootloader [0044, see first stage bootloader]; a second non-volatile memory configured to store a second bootloader [0044, see second stage bootloader]; and a microprocessor configured to: control, responsive to executing the first bootloader, the volatile memory to receive an updated second bootloader and provide the updated second bootloader to the second non-volatile memory, control the second non-volatile memory to update the second bootloader with the updated second bootloader; [0043 – 0045. See processor as well as memory and first and second stage bootloaders]; invalidate a validity signature associated with the second bootloader prior to replacing the second bootloader with the updated second bootloader; [0031, “…cryptographic signature verification algorithm for verifying a cryptographic signature of data stored in a region of the memory. It may comprise instructions for authenticating the second-stage bootloader…”]; and replace the second bootloader with the updated second bootloader [0035, see “…causing the processor to write the replacement second-stage bootloader to the inactive second-stage region…”]. Regarding claim 2, the bootloader system of claim 1, wherein the volatile memory is random-access memory [0044, show RAM]. Regarding claims 3 and 13, the bootloader system of claim 1, wherein the first non-volatile memory and the second non-volatile memory are each flash memory [0044, shows non-volatile and volatile memory]. Regarding claim 4, the bootloader system of claim 1, wherein the microprocessor includes the volatile memory and the first non-volatile memory [0044]. Regarding claim 5, the bootloader system of claim 1, wherein the second non-volatile memory is external to the microprocessor [0043 – 0045]. Regarding claim 6, the bootloader system of claim 1, wherein the microprocessor is further configured to copy, responsive to executing the first bootloader, the second bootloader from the second non-volatile memory to the volatile memory [0039, see copy replacement]. Regarding claims 7 and 14, the bootloader system of claim 1, wherein the microprocessor is further configured to write, responsive to executing the second bootloader in the volatile memory, the updated second bootloader to the second non-volatile memory [0038 – 0044, see related text previous disclosed in previously recited sections]. Regarding claims 8 and 20, the bootloader system of claim 7, wherein the microprocessor is further configured to replace, responsive to executing the second bootloader in the volatile memory and responsive to writing the updated second bootloader to the second non-volatile memory, the second bootloader with the updated second bootloader [0038 – 0044, shows first and second bootloader as well as copying/replacing and updating]. Regarding claims 9,16 and 22, the bootloader system of claim 8, wherein the microprocessor is further configured to write, responsive to replacing the second bootloader with the updated second bootloader, a validity signature associated with the updated second bootloader to the second non- volatile memory [0031, see updating and also signature]. Regarding claims 11 and 24, the bootloader system of claim 1, wherein the second non-volatile memory is configured to store an application, and wherein the microprocessor is configured to execute the application while the second bootloader is being updated [0038 – 0044]. Regarding claim 15, the method of claim 14, further comprising replacing, responsive to executing the second bootloader in the volatile memory and responsive to writing the updated second bootloader to the second non-volatile memory, the second bootloader with the updated second bootloader [0038 – 0044, shows first and second bootloader as well as copying/replacing and updating]. Regarding claim 19, the one or more non-transitory computer-readable media of claim 18, the computer-implemented method further comprising copying, responsive to executing the first bootloader, the second bootloader from the second non-volatile memory to the volatile memory [0043 – 0045]. Regarding claim 21, the one or more non-transitory computer-readable media of claim 20, the computer-implemented method further comprising replacing, responsive to executing the second bootloader in the volatile memory and responsive to writing the updated second bootloader to the second non-volatile memory, the second bootloader with the updated second bootloader [0038 – 0044, shows first and second bootloader as well as copying/replacing and updating]. Response to Arguments Applicant’s arguments with respect to claim(s) 1 – 9, 11 – 16, 18 – 22 and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument Correspondence Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chuck Kendall whose telephone number is 571-272-3698. The examiner can normally be reached on 10:00 am - 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung Sough can be reached on 571-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only [0060 – 0080]. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /CHUCK O KENDALL/ Primary Examiner, Art Unit 2192
Read full office action

Prosecution Timeline

Show 4 earlier events
Aug 20, 2025
Response Filed
Dec 02, 2025
Final Rejection mailed — §102
Mar 11, 2026
Examiner Interview Summary
Mar 11, 2026
Applicant Interview (Telephonic)
Jun 02, 2026
Request for Continued Examination
Jun 04, 2026
Response after Non-Final Action
Jun 12, 2026
Non-Final Rejection mailed — §102
Aug 17, 2026
Interview Requested

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.8%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 927 resolved cases by this examiner. Grant probability derived from career allowance rate.

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