Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this office action.
Claim Objections
Claims 1 and 6 are objected to because of the following informalities: the claims cite “toffli” gates instead of “toffoli” gates. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 6 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claim recites applying an "n+1-qubit Toffoli gate". As n increases, the physical implementation of a multi-control Toffoli gate becomes exponentially difficult and is not currently a "routine" operation in available quantum hardware. The specification does not provide sufficient instruction on how to physically construct or decompose this gate for large n, meaning the claim is not enabled across its full scope.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: The claims include the conditional if alpha_k=M−Sigma_{i=1,k-1}alpha_i=1". The variable "M" is not defined within the claim, leaving the scope of the conditional operation unclear.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: executing an "IO Operator". This is a coined term not recognized in standard quantum computing literature. While the specification defines it as a specific matrix, the claim itself lacks the structural definition of the operator. A person of ordinary skill in the art (PHOSITA) would not know the specific unitary transformation required simply by the name "IO Operator."
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) initializaing registers, determining a value, applying unitary transformations (Toffoli gates, S-Operators, IO operators). This judicial exception is not integrated into a practical application because courts have found mathematical formulas and algorithms for data manipulation are abstract ideas. The “insert operation” described is a fundamental functional concept of database management. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the use of a "quantum circuit" or "quantum method" merely provides a generic environment for executing the algorithm. While the specification argues that this allows for a "greater amount of data" not achievable by classical computers, the claims themselves do not describe a specific improvement to the physical hardware. Instead, they recite a sequence of well-known quantum logic gates (Toffoli, CNOT, X gates) to perform the calculation. This is considered "well-understood, routine, and conventional activity" within the field of quantum computing.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by El Euch et al. (U.S. Patent No. 11,093,850).
Regarding claim 1, Replace1 teaches a quantum method, comprising: initializing, by the quantum circuit, three registers in a quantum circuit (col. 3, lines 45-52); determining, by the quantum circuit, a value of α.sub.k (col. 3, lines 14-20); if α.sub.k=M−Σ.sub.i=1,k-1α.sub.i=1, then the quantum method further comprises: applying a set of size n of 3-qubit Toffoli gate (col. 3, lines 21-25).
Regarding claim 2, Replace1 teaches wherein the registers include |QDB, |S, and |D (fig. 2).
Regarding claim 3, Replace1 teaches wherein the register |D is an input register with a particular number of qubits (col. 3, lines 14-17).
Regarding claim 4, Replace1 teaches wherein the register |QDB represents a register of n qubits initialized with the vacuum state |000 . . . 0 (col. 3, lines 60-67).
Regarding claim 5, Replace1 teaches wherein the register |S represents a two qubit quantum control register initialized with state |01 (col. 2, lines 11-20).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON HOFFMAN whose telephone number is (571)272-3863. The examiner can normally be reached Monday-Friday 8:30AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Pwu can be reached at (571)272-6798. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON HOFFMAN/Primary Examiner, Art Unit 2433
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