DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks filed 12 August 2026 have been fully considered. The amendments overcome the rejection under section 101, as using the claimed quantum circuit to update a quantum database appears to integrate the claimed quantum circuit into a practical application representing an improvement in the technology of quantum circuits. However, the improvement is to a specific quantum circuit, and the claimed quantum circuit lacks characteristics of the disclosed quantum circuit such that the full breadth of the claimed quantum circuit contains subject matter wouldn’t be recognized by one of ordinary skill in the art at the time of filing as being in Applicant’s possession based off the disclosure as originally filed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Applicant has disclosed a particular arrangement of quantum logic gates applied to particular quantum registers and qubits in order to update a quantum database. Specification ¶¶ [0013]-[0022]. However, the claims recite an application of the recited quantum logic gates to a generic arrangements of quantum registers and qubits, such that there is no indication that such an algorithm would produce the results achieved by Applicant, such that one of ordinary skill in the art would not have understood Applicant to be in possession of the claimed generic algorithm.
Each limitation is presented in generic form without adequate support in the specification for the entire claimed breadth. MPEP § 2161.01.
For instance, the limitation, “initializing, by a quantum circuit, registers and two qubits in the quantum circuit” is generic over all quantum circuits with any number of registers and two qubits. However, the disclosed quantum circuit has four registers and two qubits. Fig. 2. Moreover, the disclosed registers and qubits are not generic, but a) are specific – a disclosed register of the claimed register is not simply a generic register but a |QDB〉 register that is used to hold a uniform/weighted superposition quantum database at hand, etc., and b) that have a particular size relationship between the registers - |QDB〉 is bigger than |qr〉, and |QDB〉 is bigger than both |cb〉 and |nr〉, which are of the same size. There is nothing to suggest to one of ordinary skill in the art that Applicant was in possession of an embodiment having any registers having any sizes other than the disclosed registers having the disclosed sizes.
Similarly, the claims recite “applying, by the quantum circuit, a first S operator.” However, the disclosure does not disclose generic application of an S operator, but specific operation of an S operator, namely applying the S operator in a particular manner on the |QDB〉 and |qr〉 registers. Specification ¶ [0015]. There is nothing to indicate to one of ordinary skill in the art that Applicant was in possession of an invention that applied an S operator in a different fashion or on different registers such that said application would result ultimately in a series of qubits suitable for writing the value of the qubits as an update to a quantum database as required by the claim.
That is, in general, Applicant has invented a specific set of quantum registers having a specific sequence of specific quantum gates applied thereto in a specific manner that achieves a specific purpose, yet the claims are directed to a generic set of quantum registers having a specific sequence of quantum gates applied thereto in a generic manner. The disclosure does not contain an adequate number of species to establish that Applicant is in possession of generic registers or generic application of specific quantum gates.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 15 recite “searching, by the quantum circuit, database data in register |QDB〉 that matches criteria specified in register |qr〉” and “applying, by the quantum circuit, a first S operator.” Per the disclosure, the latter appears to be an envisioned way of doing the former. Specification ¶ [0015]. It is therefore unclear whether these are two separate limitation or the same limitation. For the purposes of examination, they will be read as reciting the same step.
Conclusion
The prior art does not teach the claimed quantum circuit. The use of the claimed quantum circuit represents an improvement to technology. The claimed quantum circuit is broader than the quantum circuit that was disclosed, and therefore lacks adequate written description. The disclosure describes 8 steps being applied to particular quantum registers having been initialized with particular information. Specification ¶¶ [0013]-[0023]. Claims directed to these 8 specific disclosed steps applied to the 6 specific disclosed quantum registers (a “qubit” is a register of size 1 qubit) would be allowable.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM SPIELER whose telephone number is (571)270-3883. The examiner can normally be reached Monday-Friday, 11-3.
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WILLIAM SPIELER
Primary Examiner
Art Unit 2159
/WILLIAM SPIELER/Primary Examiner, Art Unit 2159
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