Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
FINAL REJECTION
This Office Action addresses U.S. Patent Application No. 18/221,305, which is filed as a reissue of U.S. Patent Application No. 16/460,271 (hereinafter, the '271 application), which issued as U.S. Patent No. 11,061,577 (hereinafter, the '577 patent), entitled “SYSTEM ON CHIP PERFORMING TRAINING OF DUTY CYCLE OF WRITE CLOCK USING MODE REGISTER WRITE COMMAND, OPERATING METHOD OF SYSTEM ON CHIP, ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP”.
Claims 1-40 are pending.
Claims 1-20 were issued in the '577 patent.
Claims 21-40 are newly presented with this reissue application.
PRIOR OR CONCURRENT PROCEEDINGS
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which the patent is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
In accordance with MPEP § 1406, the examiner has reviewed and considered the prior art made of record during the prosecution of the original patent. Such prior art need not be resubmitted in this reissue application unless applicant desires the information to be printed on a patent issuing from this reissue application.
SPECIFICATION
The previous objection to the specification is withdrawn due to the amendment filed February 6, 2026.
CLAIM OBJECTIONS
The previous objection to claim 3 is withdrawn due to the remarks submitted with the amendment filed February 6, 2026.
The previous objections to claims 19 and 23 are withdrawn due to the amendment filed February 6, 2026.
Claims 11 and 21-40 are objected to because:
(1) Claim 11 is objected to because in lines 4 and 5, “code being used … and which is used for” is not grammatically correct. The following language is suggested for lines 4 and 5: “code being used (1) to adjust a duty cycle of a third clock which is generated within the memory device based on a second clock generated from the system on chip and (2) for a data”.
(2) Claims 21-40 are objected to because the amendment filed February 6, 2026 proposes amendments to claims 21-40 that do not comply with 37 CFR 1.173(b), which sets forth the manner of making amendments in reissue applications. Note MPEP 1453(IV), “all underlining and bracketing in the reissue application should be made relative to the text of the patent, as follows. In accordance with 37 CFR 1.173(g), all amendments in the reissue application must be made relative to (i.e. vis-à-vis) the patent specification in effect as of the date of the filing of the reissue application.”
Appropriate correction is required.
CLAIM REJECTIONS - 35 USC § 112, 2nd PARAGRAPH
The previous rejections of claims 1-35 and the first of two previous rejections of claim 36 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn due to the amendment.
Claims 36-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In claim 36, line 12, the scope of “find” unclear as to whether it is a search of stored options or whether it is a calculation.
The dependent claims 37-40 are rejected as being dependent upon independent claim 36 rejected above.
OBJECTIONS BASED ON DEFECTIVE OATH/DECLARATION
The statement of error in the declaration filed February 6, 2026 is as follows:
“Claim 1 of U.S. Patent No. 11,061,577 includes an error under 35 U.S.C. 12(b) in which recitation of "the memory device receiving the command" is indefinite.
New claim 21 in the instant reissue is broader/different in scope than the original claims. Independent claim 1 of the original U.S. Patent No. 11,061,577 recites "a second clock generator configured to generate a second clock to be sent to the memory device." These features are not recited in new claim 21. All errors being corrected in this reissue application arose without any deceptive intention on the part of the Applicant.”
The reissue oath/declaration filed with this application is objected to because of the following:
The statement of error references subject matter surrendered during the prosecution of the original patent: "a second clock generator configured to generate a second clock to be sent to the memory device." The inclusion of surrendered subject matter in the original patent claims is not an error and therefore not a basis for reissue.
REJECTIONS BASED ON DEFECTIVE OATH/DECLARATION
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. §251 that form the basis for the rejections under this section made in this Office action:
(a) IN GENERAL.—Whenever any patent is, through error, deemed wholly or partly inoperative or invalid, by reason of a defective specification or drawing, or by reason of the patentee claiming more or less than he had a right to claim in the patent, the Director shall, on the surrender of such patent and the payment of the fee required by law, reissue the patent for the invention disclosed in the original patent, and in accordance with a new and amended application, for the unexpired part of the term of the original patent. No new matter shall be introduced into the application for reissue.
Defective Reissue Declaration
The previous rejection based upon a defective reissue declaration under 35 U.S.C. §251 is withdrawn due to the declaration filed February 6, 2026.
While the new declaration is objected to for referencing subject matter surrendered during the prosecution of the original patent, it is not defective under 35 U.S.C. §251, because it includes at least one error that qualifies as a basis for reissue: “Claim 1 of U.S. Patent No. 11,061,577 includes an error under 35 U.S.C. 12(b) in which recitation of ‘the memory device receiving the command’ is indefinite”.
Impermissible Recapture
Claims 21-40 lack subject matter surrendered during the prosecution of the '577 application.
Independent claims 21, 28 and 36 lack the following language of the original claims which was argued to overcome rejections based on the prior art in remarks filed on February 24, 2021, during the prosecution of the '271 application:
With regard to claim 16:
“system on chip configured to generate a first clock and a second clock having a frequency higher than a frequency of the first clock” (Remarks, page 2)
“memory device synchronized with the first clock and the second clock output from the system on chip” (Remarks, page 3)
“second clock having a frequency higher than a frequency of the first clock,” (Remarks, page 3)
“second clock and third clock” (Remarks, page 3)
“command and code synchronized with the first clock signal” (Remarks, page 4)
value to set “a duty cycle” (Remarks, page 4)
Each of the limitations cited above were surrendered during the prosecution of the '271 application, in response to the non-final Office action mailed on December 8, 2020 in the '271 application, wherein claim 16 was rejected based on prior art and claims 17-20 were objected to as being dependent on claim 16.
Independent claims 21, 28 and 36 lack the following language of the original claims which was argued to overcome rejections based on the prior art in remarks filed on November 13, 2020, during the prosecution of the '271 application:
With regard to claim 1:
“system on chip” (Remarks, pages 3 and 5)
“command and address generator” (Remarks, pages 3 and 5)
“a code for adjusting a duty cycle of a third clock … based on a code stored in the mode registers of the memory device” (Remarks, pages 3, 4, 5 and 6)
“the third clock being used for a data input/output of the memory device” (Remarks, page 3)
“a training circuit” (Remarks, page 3)
“a plurality of valid window margins for the code” (Remarks, pages 3 and 6)
“command and address generator configured to generate a code for adjusting a duty cycle of a third clock used for a data input/output of the memory device" (Remarks, page 5)
“a system on chip generating the first and second clocks sent to a memory device” (Remarks, page 5)
“data receiver included in a system on chip (to receive a data strobe signal and a data input/output signal output from the memory device)” (Remarks, page 6)
With regard to claim 2:
“wherein the command and address generator is configured to repeatedly generate the command and the code, and wherein a plurality of values of the code repeatedly generated by the command and address generator correspond to the plurality of valid window margins, respectively” (Remarks, page 6)
With regard to claim 9:
“duty cycle adjuster” (Remarks, page 7)
“duty cycle output to the memory device” (Remarks, page 7)
With regard to claim 11:
Refers to the analysis of claim 1.
With regard to claim 16:
Refers to the analysis of claim 1.
Each of the limitations cited above were surrendered during the prosecution of the '271 application, in response to the non-final Office action mailed on August 25, 2020 in the '271 application, wherein claims 1-6, 8-16 and 18 were rejected based on prior art and claims 7, 17 and 19-20 were objected to as being dependent on respective base claims.
The three step test for recapture:
Step 1 - Is There Broadening?
Are the reissue claims broader than the original patent claims in at least some respects? Yes, for example, independent claims 21, 28 and 36 lack the language cited above, which was required of the claims of '577 patent.
Step 2 - Does Any Broadening Aspect of the Reissued Claim Relate to Surrendered Subject Matter?
Substep 1 – Did applicant surrender any subject matter in the prosecution of the original application that became the patent to be reissued? Yes, the surrendered subject matter is noted above.
Substep 2 - Does the broadening in the reissue claims result from eliminating limitations surrendered in the original prosecution? Yes, independent claims 21, 28 and 36 omit limitations that the prosecution record shows as argued to overcome rejections based on prior art during the original prosecution.
Step 3 - Are the Reissue Claims Materially Narrowed in Other Respects, and Hence Avoid the Recapture Rule?
The reissue claims are not materially narrowed in other respects.
Thus, claims 21-40 are rejected under 35 U.S.C. 251 as being an impermissible recapture of broadened claimed subject matter surrendered in the application for the patent upon which the present reissue is based. In re McDonald, 43 F.4th 1340, 1345, 2022 USPQ2d 745 (Fed. Cir. 2022); Greenliant Systems, Inc. et al v. Xicor LLC, 692 F.3d 1261, 103 USPQ2d 1951 (Fed. Cir. 2022); In re Youman, 679 F.3d 1335, 102 USPQ2d 1862 (Fed. Cir. 2012); In re Shahram Mostafazadeh and Joseph O. Smith, 643 F.3d 1353, 98 USPQ2d 1639 (Fed. Cir. 2011); North American Container, Inc. v. Plastipak Packaging, Inc., 415 F.3d 1335, 75 USPQ2d 1545 (Fed. Cir. 2005); Pannu v. Storz Instruments Inc., 258 F.3d 1366, 59 USPQ2d 1597 (Fed. Cir. 2001); Hester Industries, Inc. v. Stein, Inc., 142 F.3d 1472, 46 USPQ2d 1641 (Fed. Cir. 1998); In re Clement, 131 F.3d 1464, 45 USPQ2d 1161 (Fed. Cir. 1997); Ball Corp. v. United States, 729 F.2d 1429, 1436, 221 USPQ 289, 295 (Fed. Cir. 1984). The reissue application contains claim(s) that are broader than the issued patent claims. The record of the application for the patent family shows that the broadening aspect (in the reissue) relates to claimed subject matter that applicant previously surrendered during the prosecution of the application. Accordingly, the narrow scope of the claims in the patent was not an error within the meaning of 35 U.S.C. 251, and the broader scope of claim subject matter surrendered in the application for the patent cannot be recaptured by the filing of the present reissue application.
Original Patent Requirement
The previous rejections under the original patent requirement of 35 USC § 251 are withdrawn due to the amendment filed February 6, 2026.
DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
For the reasons described above, new claims 21-40 are not eligible for reissue under 35 USC § 251 as presently written.
Regarding original claims 1-20,
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,003,370. Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons described below.
Note that all of the features of the system on chip claim 1 of the present reissue application are taught or suggested by claim 8 of U.S. Patent No. 11,003,370, wherein it would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize multiple clocks in conjunction with the multiple codes, in order to adjust the duty cycles that depend on the multiple codes:
U.S. Application No. 18/221,305
U.S. Patent No. 11,003,370
1. A system on chip comprising:
a first clock generator configured to generate a first clock to be sent to a memory device;
a second clock generator configured to generate a second clock to be sent to the memory device;
a command and address generator configured to generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock, and generate a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device;
a data receiver configured to receive a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock; and
a training circuit configured to calculate a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.
8. A system on chip comprising:
a clock generator configured to adjust a duty cycle of a clock to be output to a memory device depending on a first code;
a reference voltage generator configured to adjust a first level of a first reference voltage used to determine a first data input/output signal output from the memory device depending on a second code;
a data receiver configured to align a first data strobe signal and the first data input/output signal output from the memory device, when one of the first code and the second code is changed; and
a processor configured to calculate a plurality of read valid window margins for a plurality of combinations of the first code and the second code based on the first data strobe signal and the first data input/output signal,
wherein the aligning the first data strobe signal and the first data input/output signal, the adjusting the duty cycle, and the adjusting the first level, are performed simultaneously.
Note that all of the features of method claim 11 of the present reissue application are taught or suggested by claim 1 of U.S. Patent No. 11,003,370, wherein for the duty cycle of the clock and the first level of the first reference voltage of the system on chip to be set, the target values must necessarily be sent to the memory device:
U.S. Application No. 18/221,305
U.S. Patent No. 11,003,370
11. An operating method of a system on chip connected with a memory device, the method comprising:
changing a code to be sent to the memory device in synchronization with a first clock, the code being used to adjust a duty cycle of a third clock which is generated within the memory device based on a second clock generated from the system on chip, and is used for a data input/output of the memory device;
calculating a plurality of valid window margins for the code based on a data strobe signal and a data input/output signal output from the memory device receiving the code; and
sending a target value of the code corresponding to a maximum valid window margin of the plurality of valid window margins to the memory device.
1. An operating method of a system on chip connected with a memory device, the method comprising:
changing one of a first code for adjusting a duty cycle of a clock to be provided to the memory device or a second code for adjusting a first level of a first reference voltage of the system on chip used to determine a first data input/output signal output from the memory device;
aligning a first data strobe signal and the first data input/output signal output from the memory device;
calculating a plurality of read valid window margins for a plurality of combinations, each one of the plurality of combinations being a pair of one of values of the first code and one of values of the second code, based on the first data strobe signal and the first data input/output signal; and
setting the duty cycle of the clock and the first level of the first reference voltage of the system on chip, respectively, based on a first target value of the first code and a second target value of the second code corresponding to a maximum read valid window margin of the plurality of read valid window margins,
wherein the changing the one of the first code or the second code, the aligning the first data strobe signal and the first data input/output signal, and the setting the duty cycle, are performed simultaneously.
Note that all of the features of the electronic device claim 16 of the present reissue application are taught or suggested by claim 16 of U.S. Patent No. 11,003,370, wherein it would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize multiple clocks for the first, second and third trainings, since different speeds/frequencies would have been required in different trainings:
U.S. Application No. 18/221,305
U.S. Patent No. 11,003,370
16. An electronic device comprising:
a system on chip configured to generate a first clock and a second clock having a frequency higher than a frequency of the first clock; and
a memory device synchronized with the first clock and the second clock output from the system on chip,
wherein the system on chip is further configured to:
generate a command and a code synchronized with the first clock; and
train a duty cycle of a third clock which is generated within the memory device based on the second clock and is used for a data input/output of the memory device, by sending the command and the code to the memory device.
16. An electronic device comprising:
a system on chip configured to generate a clock; and
a memory device synchronized with an output from the clock,
wherein the system on chip is further configured to simultaneously perform a first training of a duty cycle of the clock adjusted according to a first code,
a second training of a first level of a first reference voltage of the system on chip which is adjusted according to a second code and is used to determine a first data input/output signal output from the memory device, and
a third training of a first skew between a first data strobe signal and the first data input/output signal output from the memory device.
Likewise, the dependent claims are taught similarly as they include many of the overlapping features of these claims.
PRIOR ART
For the reasons described above, new claims 21-40 are not eligible for reissue under 35 USC § 251 as presently written.
Regarding original claims 1-20, other than U.S. Patent No. 11,003,370 noted in the double patenting rejections above, the following references are among those most relevant to the claims:
(1) Eckhardt et al., U.S. Patent No. 6,583,657, (cited during the prosecution of the original patent) teaches a duty cycle correction circuit that is configured to adjust the duty cycle of a clock signal in a clock distribution network.
(2) Huang, U.S. Patent No. 8,665,665, teaches a duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to a comparison signal. Note, for example, Figure 3 of Huang:
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(3) Okuda et al., U.S. Patent No. 6,704,879, teaches a clock generation circuit including a clock duty adjusting circuit.
(4) Jeon, U.S. Patent No. 8,760,945, teaches a controller that may alter a signal power, a terminal impedance (e.g., an adjustable on die termination (pull-up and/or in series) of the controller and/or the memory device, and/or a duty cycle of the command/address calibration signal.
However, none of the references cited by the examiner or by applicant appear to teach or suggest, either alone or in combination, each and all of the features of claims 1-20.
Regarding claim 1, the prior art does not teach or suggest the claimed a system on chip comprising:
a first clock generator configured to generate a first clock to be sent to a memory device;
a second clock generator configured to generate a second clock to be sent to the memory device;
a command and address generator configured to generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock, and generate a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device;
a data receiver configured to receive a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock; and
a training circuit configured to calculate a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.
Regarding claim 11, the prior art does not teach or suggest the claimed operating method of a system on chip connected with a memory device, the method comprising:
changing a code to be sent to the memory device in synchronization with a first clock, the code being used to adjust a duty cycle of a third clock which is generated within the memory device based on a second clock generated from the system on chip, and is used for a data input/output of the memory device;
calculating a plurality of valid window margins for the code based on a data strobe signal and a data input/output signal output from the memory device receiving the code; and
sending a target value of the code corresponding to a maximum valid window margin of the plurality of valid window margins to the memory device.
Regarding claim 16, the prior art does not teach or suggest the claimed electronic device comprising:
a system on chip configured to generate a first clock and a second clock having a frequency higher than a frequency of the first clock; and
a memory device synchronized with the first clock and the second clock output from the system on chip,
wherein the system on chip is further configured to:
generate a command and a code synchronized with the first clock; and
train a duty cycle of a third clock which is generated within the memory device based on the second clock and is used for a data input/output of the memory device, by sending the command and the code to the memory device.
RESPONSE TO ARGUMENTS
The arguments submitted with the amendment filed February 6, 2026 have been carefully considered. Accordingly:
The previous objection to the specification is withdrawn due to the amendment filed February 6, 2026.
The previous objection to claim 3 is withdrawn due to the remarks submitted with the amendment filed February 6, 2026.
The previous objections to claims 19 and 23 are withdrawn due to the amendment filed February 6, 2026.
New objections to claims 11 and 21-40 are made due to the amendment filed February 6, 2026.
The previous rejections of claims 1-35 and the first of two previous rejections of claim 36 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn due to the amendment.
The second of two previous rejections of claim 36 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is maintained.
The previous objections to the declaration are withdrawn in view of the new declaration filed February 6, 2026.
The declaration filed February 6, 2026 is objected to.
The previous rejection based upon a defective reissue declaration under 35 U.S.C. §251 is withdrawn due to the new declaration filed February 6, 2026.
The rejection of claims 21-40 under 35 U.S.C. §251 for lack of subject matter surrendered during the prosecution of the '577 application is maintained.
Applicant argues, “Applicant respectfully traverses these assertions. Applicant notes that the remarks filed in the February 24, 2021 response pertain to claim 16 of U.S. Patent No. 11,061,577. Applicant submits that the claimed features referenced on page 7 of the Office Action are not included in claim 1 of U.S. Patent No. 11,061,577, which was allowed at the time of filing the February 24, 2021 response. As a result, the claimed features referenced on page 7 of the Office Action are not required to be recited in claims 21-40 to rebut the assertion that claims 21-40 attempt to recapture surrendered subject matter.”
This argument is not convincing. First, all of claims 21-40 cannot be immune to the surrendered subject matter of claim 16. Second, each of the original patent claims have surrendered subject matter, including claim 1.
Applicant further argues, “Applicant submits that claims 21-40 clearly meet Step 3 since claims 21-40 recite materially narrowed features. For example, claim 21 recites features that were not recited in issued claims 1-20 such as ‘issuing, by a controller, a first mode register write command to a memory device to cause a first value to be written to a mode register to perform training for adjusting a duty cycle of a first clock;’ ‘issuing, by the controller, a read command to read test data;’ and ‘issuing, by the controller, a second mode register write command to cause a second value to be written to the mode register to obtain one of a plurality of values for a code that is sent to the memory device to adjust the duty cycle of the first clock.’ Applicant submits that as these features were not previously recited in the issued claims, the combination of these features materially narrows claim 21, and thus, avoids the recapture rule.”
This argument is not convincing: (1) regarding the “mode register write command” “to perform training for adjusting a duty cycle of a first clock”, note original claims 10 and 19; (2) regarding the “read command to read test data”, note original claim 13; and (3) regarding the “second mode register write command”, note that adding a second one of the “mode register write command” of original claims 10 and 19 would not be materially narrowing.
The double patenting rejections of claims 1-20 are maintained.
Applicant argues, “Applicant submits that claims 1-20 of the present application are patentably distinct from claims 1-20 of U.S. Patent No. 11,003,370. For example, claim 1 of the present application recites features that are not recited in U.S. Patent No. 11,003,370 such as "a second clock generator configured to generate a second clock to be sent to the memory device;" and "a command and address generator configured to generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock, and generate a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device."
Similarly, claim 11 of the present application is patentably distinct from the claims of U.S. Patent No. 11,003,370. For example, claim 11 recites the features of "sending a target value of the code corresponding to a maximum valid window margin of the plurality of valid window margins to the memory device," which is not recited in the claims of U.S. Patent No. 11,003,370.
Furthermore, claim 16 recites features not recited in the claims of U.S. Patent No. 11,003,370 such as generating "a command and a code synchronized with the first clock" and training, "by sending the command and the code to the memory device, a duty cycle of a third clock which is generated within the memory device based on the second clock and is used for a data input/output of the memory device.”
These arguments are not convincing. Applicant has not addressed the obviousness position set forth in the rejections.
CONCLUSION
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to B. James Peikari at telephone number (571)272-4185. The examiner can normally be reached on Mon-Fri from 8:30am to 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Kosowski, SPE Art Unit 3992, can be reached at 571-272-3744.
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Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to the Central Reexamination Unit at telephone number (571) 272-7705.
/B. James Peikari/
Primary Examiner, Art Unit 3992
Conferees:
/C. Michelle Tarae/Reexamination Specialist, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992