DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-35 are pending in this application. Claims 3, 5, 12, 14, 16-17, and 21-23 are cancelled. Claims 28-35 are new.
Election/Restrictions
Claims 4-5 and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species 1, there being no allowable generic or linking claim. After thorough examination, it was determined that due to claims 4-5 and 16 reciting limitation “second power stage attached to a second surface of the first substrate” which is only drawn to nonelected Species 1, they are withdrawn. Election was made without traverse in the reply filed on 08/21/2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 07/13/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendments filed 07/21/26 have been received and made of record.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings were received on 07/13/2023.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
first high side switch circuitry and first low side switch circuitry and second high side circuitry and second low side switch circuitry of claim 29
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-8, 10-11, 15, 18-20, 24-31 and 33-35 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chen et al. (US20230137975 A1) hereinafter Chen, and further in view of Cho et al. (US9515014 B2) hereinafter Cho. Regarding claim 1 and 15, Chen discloses a multi-phase power converter and method (fig 45, 4-Phase Buck Unit comprising phases with inductors (L1, L2, L4) and power stages QH1/QL1 driven by a multi-stage 2:1 SC Unit front-end; par [0147] explains that the example embodiment is of a four-phase but any number of phases can be implemented; fig 1, voltage regulator module 10; fig 2 topology layout; claim 1) comprising: a first power converter phase (fig 45, Buck unit phase uses power stages QH1, QL1 and inductor L1; fig 1, DrMOS), including a first power stage circuit (par [0118] describes the first stage of a two stage converter topology “first stage of the converter is a 2:1 resonant switched-capacitor circuit”; fig 1, DrMOS 22 power stage circuits/switches; fig 45, high/low-side power switches e.g. QH1/QL1) and a first inductor (abstract; claim 1; par [0116] explains inductor placement to allow vertical current; fig 1, one of the coupled inductors 16; fig 45, L1); a second power converter phase (claim 1; fig 1, GaN, fig 45, QH2/QL2) including a second power stage (par [0118] describes “The second stage of the converter is a 24:1 four-level series capacitor buck converter”; par [0197] describes a second power converter stage, fig 45 Q3/Q4) and a second inductor (abstract; claim 1;par [0116] coupled inductors; fig 1, one of the coupled inductors 16); and a first substrate extending along a first substrate plane (claim 1; figs 1-3, PCB2 14; par [0122]) in which: i) the first power stage circuit, the first inductor, and the second inductor are arranged above the first substrate (claim 1; par [0009]; par [0122]; par [0123]; par [0124]; fig 2, circuit module and coupled inductor components arranged on top PCB2 14, power source components on bottom PCB not labeled), and ii) the second power stage circuit is arranged below the first substrate (claim 1 “at least one power source placed below the bottom PCB”; par [0124] describes the semiconductor switches and controllers are placed on the bottom two PCBs); and wherein at least a portion of the first substrate is disposed between the first power stage circuit and the second power stage circuit (Chen fig 2 appears that it may suggest such an arrangement 14 PCB2 also claim 1 “at least one power source placed below the bottom PCB”; par [0124] describes the semiconductor switches and controllers are placed on the bottom two PCBs; par [0122] “bottom PCB 14 as the small-scale power board which only hosts the power devices”; fig 2, examiner interprets that the bottom two PCBs contain power devices which the top 14 PCB2 would be placed in between the power devices of a variable number of phases).
Alternatively, Cho discloses a power converter package with multiple substrate surfaces and power stage components arranged on the multiple substrate surfaces. Cho discloses wherein at least a portion of the first substrate (fig 4A, patterned conductive carrier 450 having top surface 452 and bottom surface 454) is disposed between the first power stage (fig 4A, power stage with components switch node segment 450a and output segment 450b) and the second power stage (fig 4A, FET 410 /Q.sub.1 and FET 420 (Q.sub.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen and incorporate the use of multiple layers and substrates with power stage components on each surface as taught by Cho. The advantage of this design is for space saving capabilities within the integrated circuit.
Regarding claim 2, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein the first power stage circuit and the second power stage circuit at least partly overlap each other in a vertical direction, wherein the vertical direction is substantially perpendicular to the first substrate plane (Chen figs 1 and 2, vertical components on top PCB2 14 DrMOS 22 appear to overlap components on bottom PCB appearing perpendicular to the horizontal configured PCBs; fig 1, power DrMOS components 22 overlap GaN components).
Regarding claim 6, Chen and Cho disclose a multi-phase power converter (Chen fig 1, voltage regulator module 10; fig 2; claim 1, fig 45) comprising: a first power converter phase (Chen claim 1; par [0147] explains that the example embodiment is of a four-phase but any number of phases can be implemented; fig 45 shows ) including a first power stage (Chen par [0196] describes the first stage of a two stage converter topology; fig 45, 4 phase Buck unit uses power stages QH1, QL1 and inductor L1; fig 1, DrMOS) and a first inductor (Chen abstract; claim 1;par [0116] explains inductor placement to allow vertical current; figs 1 and 2 show coupled inductor 16 connected to DrMOS 22 and GaN power stage circuits); a second power converter phase including a second power stage and a second inductor (Chen (claim 1; fig 1, GaN, fig 45, QH2/QL2; par [0118] describes “The second stage of the converter is a 24:1 four-level series capacitor buck converter”; par [0197] describes a second power converter stage, fig 45 Q3/Q4; par [0116] coupled inductors; fig 1, one of the coupled inductors 16); and a first substrate extending along a first substrate plane (Chen claim 1; figs 1-3, PCB2 14; par [0122]) in which: i) the first power stage, the first inductor, and the second inductor are arranged above the first substrate (Chen claim 1; par [0009]; par [0122]; par [0123]; par [0124]; DrMOS 22 and coupled inductor components 16 arranged on top PCB2 14, power source components GaN on bottom unlabeled in fig 2), and ii) the second power stage is arranged below the first substrate (Chen claim 1 “at least one power source placed below the bottom PCB”; par [0124] describes the semiconductor switches and controllers are placed on the bottom two PCBs); the multi-phase power converter further comprising: a second substrate extending along a second substrate plane (Chen fig 2, bottom substrate below PCB2 14), wherein the first power stage is attached to a first surface of the first substrate (Chen par [0123] three vertical stacked PCBs are shown in fig 2, the circuit on the bottom two PCBs 14 are switching devices, and the top PCB 12 hosts the microprocessor and the output capacitors of the VRM. Three coupled inductors 16 are placed between the top PCB 12 and the bottom PCB2 14, GaN components are between PCB2 14 and bottom substrate), wherein the second power stage is attached to a first surface of the second substrate (Chen see fig 2, the various switching devices on top surface of top PCB2 14 e.g. DrMOS and switching devices on bottom substrate GaN can each represent a converter stage), and wherein at least a part of the first substrate is arranged between the first power stage and the second power stage (Chen fig 2, PCB2 14 with switching devices DrMOS on top of PCB2 14 and GaN below; alternatively Cho fig 4A, patterned conductive carrier 450 having top surface 452 and bottom surface 454 with power stage components switch node segment 450a and output segment 450b and FET 410 /Q.sub.1 and FET 420/Q.sub.2).
Regarding claim 7, Chen and Cho disclose the multi-phase power converter as in claim 6 further comprising at least one capacitive element attached to the first surface of the first substrate (Chen par [0123] output capacitors 20 Cout).
Regarding claim 8, Chen and Cho disclose the multi-phase power converter as in claim 7 further comprising at least one capacitive element attached to the first surface of the second substrate (Chen fig 1 and 2, Capacitive elements C.sub.in, C.sub.sc, and C.sub.m in PCB14).
Regarding claim 10, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein the first inductor (Chen fig 2, coupled inductor 16) is arranged above the first power stage circuit (Chen abstract; claim 1;par [0116] explains inductor placement to allow vertical current) and electrically connected to a switching node of the first power stage circuit (Chen par [0164] “coupled inductors with cross-coupled switching”), and wherein the second inductor (Chen fig 2 coupled inductor 16) is arranged above the second power stage circuit (Chen abstract; claim 1;par [0116] explains inductor placement to allow vertical current) and electrically connected to a switching node of the second power stage circuit (Chen par [0164] “coupled inductors with cross-coupled switching”).
Regarding claim 11, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein the first substrate comprises a through-hole for establishing an electrical connection between the second power stage circuit and the second inductor (Chen claim 15, describes the magnetic core having a center leg with a hole there through containing a wire, a current of the wire being adjustable, and/or wherein the magnetic core has one of a cubic and cylindrical shape; par [0128]; par [0153]).
Regarding claim 18, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein the first inductor is arranged above the first power stage and is electrically connected to the first power stage (Chen figs 1 and 2, inductor 16 arranged above PCB14 is electrically connected to switching devices 22 on PCB14 upper and PCB14 lower); and wherein the second inductor is arranged above the second power stage and is electrically connected to the second power stage (Chen figs 1 and 2, coupled inductor 16 is connected to multiple switching devices on both PCB14 upper and lower).
Regarding claim 19, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein the first power stage circuit is disposed between the first substrate and the first inductor (Chen figs 1 and 2, inductors 16 and top PCB14 is above switching components 22 on bottom PCB14).
Regarding claim 20, Chen and Cho disclose the multi-phase power converter as in claim 19, wherein the first power stage circuit includes a first side operative to supply current to the first inductor; and wherein the first power stage circuit includes a second side in contact with the first substrate (Chen Abstract; pars [0118], [0119], and [0123] describe a two stage converter architecture arrange with the power stages on the bottom two PCB14 of fig 2 but not limited to three PCBs and alternate arrangements of power stage components are possible; see figs 1 and 2, connections from the switching devices 22 to the inductor 16 “multiphase coupled inductor is configured to deliver current vertically from the bottom PCB to the top PCB”).
Regarding claim 24, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein at least a portion of the first power stage circuit is disposed between the second inductor and the first substrate (Chen figs 1 and 2, inductors on PCB14 are above switching devices 22 and the top PCB14 is below the switching devices 22).
Regarding claim 25, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein a first portion of the first power stage circuit resides between a first portion of the first substrate and the second inductor; and wherein the first portion of the first substrate resides between the first portion of the first power stage circuit and a first portion of the second power stage circuit (Chen figs 1 and 2, see switching devices 22 on top and bottom PCB14 which are power stage devices, the inductor 16 is above all power devices; alternatively see Cho fig 4A, patterned conductive carrier 450 having top surface 452 and bottom surface 454 is disposed between power stage with components switch node segment 450a and output segment 450b and a second power stage FET 410 /Q.sub.1 and FET 420/Q.sub.2).
Regarding claim 26, Chen and Cho disclose the multi-phase power converter as in claim 25, wherein a second portion of the first power stage circuit resides between a second portion of the first substrate and the first inductor; and wherein the second portion of the first substrate resides between the second portion of the first power stage circuit and a second portion of the second power stage circuit (Chen figs 1 and 2 see switching devices 22 on top and bottom PCB14 which are power stage devices, the inductor 16 is above all power devices; alternatively see Cho fig 4A, patterned conductive carrier 450 having top surface 452 and bottom surface 454 is disposed between power stage with components switch node segment 450a and output segment 450b and a second power stage FET 410 /Q.sub.1 and FET 420/Q.sub.2).
Regarding claim 27, Chen and Cho disclose the multi-phase power converter as in claim 26, wherein the second portion of the first power stage circuit is adjacent to the first portion of the first power stage circuit; wherein the second portion of the first substrate is adjacent to the first portion of the first substrate; wherein the second portion of the second power stage circuit is adjacent to the first portion of the second power stage circuit (Chen figs 1 and 2 see switching devices 22 on top and bottom PCB14 which are power stage devices, the inductor 16 is above all power devices; alternatively see Cho fig 4A, patterned conductive carrier 450 having top surface 452 and bottom surface 454 is disposed between power stage with components switch node segment 450a and output segment 450b and a second power stage FET 410 /Q.sub.1 and FET 420/Q.sub.2).
Regarding claim 28, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein the first power stage circuit is operative to control a flow of first current through the first inductor; wherein the second power stage circuit is operative to control a flow of second current through the second inductor; wherein the first inductor is configured to reside above the first power stage circuit and the first inductor is electrically connected to the first power stage; and wherein the second inductor is configured to reside above the second power stage circuit and the second inductor is electrically connected to the second power stage circuit via a circuit path extending through the first substrate (Chen fig 1, Coupled Inductor 16 resides physically above the 22 DrMOS power stage layer and the PCB2 14 “first substrate”, power stage components separated by PCB2 14, 22 DrMOS is above PCB2 14 and GaN switches below PCB2 14; fig. 45, shows a primary stage like a 2:1 SC Unit leading to a multi-phase Buck Unit, the GaN switches below the substrate must connect to the multi-phase buck components and Coupled Inductor 16 located above. Therefore, this electrical connection inherently requires a circuit path extending directly through the first substrate PCB2 14 via vertical vias).
Regarding claim 29, Chen and Cho disclose the multi-phase power converter as in claim 28, wherein the first power stage circuit includes first high side switch circuitry and first low side switch circuitry configured to control the flow of first current through the first inductor; wherein the second power stage circuit includes second high side circuitry and second low side switch circuitry configured to control the flow of the second current through the second inductor (Chen fig. 45 confirms that each phase of the power converter comprises high-side and low-side switch combinations e.g. QH1/QL1, QH2/QL2); wherein a first portion of the first power stage circuit is disposed between the first substrate and the first inductor; and wherein a second portion of the first power stage circuit is disposed between the first substrate and the second inductor (Chen fig. 1, 22 DrMOS layer is arranged laterally as individual phase blocks sandwiched directly between PCB2 14 and the Coupled Inductor 16 above it. A first portion e.g. one DrMOS phase circuit, sits between PCB2 14 and a first inductor channel. A second portion, another DrMOS phase circuit, sits between PCB2 14 and a adjacent second inductor channel).
Regarding claim 30, Chen and Cho disclose the multi-phase power converter as in claim 1, wherein a first portion of the first substrate is disposed between the second inductor and the second power stage circuit; and wherein a first portion of the first power stage circuit is disposed between the first portion of the first substrate and the second inductor (Chen fig. 1 explicitly shows PCB2 14 positioned underneath the Coupled Inductor 16 and directly above the GaN power stage components. Therefore, a portion of the first substrate PCB2 14 is disposed between the inductor and the second power stage circuit GaN. DrMOS 22 layered directly between PCB2 14 and the Coupled Inductor 16 “the first power stage circuit” DrMOS 22)is disposed between the first substrate and the inductor).
Regarding claim 31, Chen and Cho disclose a multi-phased power converter as in claim 30, wherein a second portion of the first substrate is disposed between the first inductor and the second power stage circuit; and wherein a second portion of the first power stage circuit is disposed between the second portion of the first substrate and the first inductor (Chen fig 45, multi-phase system e.g. 4-Phase Buck Unit utilizing a multi-phase coupled inductor design repeats laterally across multiple phases. A different lateral section "second portion" of PCB2 14 and the power stage circuits performs the exact same stacking sequence relative to a different inductor core filament within the Coupled Inductor 16 assembly).
Regarding claim 33, Chen and Cho the multi-phase power converter as in claim 1, wherein a first portion of the first power stage circuit is disposed between a first portion of the first substrate and the first inductor; wherein a second portion of the first power stage circuit is disposed between a second portion of the first substrate and the second inductor; wherein the first portion of the first substrate is disposed between a first portion of the second power stage circuit and the first portion of the first power stage circuit; and wherein the second portion of the first substrate is disposed between a second portion of the second power stage circuit and the second portion of the first power stage circuit (Chen fig 1, first power stage circuit 22 DrMOS layer is sandwiched vertically between PCB2 14 and the Coupled Inductor 16 containing the first and second inductors. PCB2 14 sits directly between the GaN components “second power stage circuit” below it and the 22 DrMOS components “first power stage circuit” above it).
Regarding claim 34, Chen and Cho disclose a multi-phase power converter in claim 33, wherein a terminal node of the first inductor is directly connected to a third portion of the first power stage, the third portion of the first power stage circuit disposed between a third portion of the first substrate and the first inductor; wherein the first power stage circuit is operative to control flow of first current through the first inductor; and wherein the second power stage circuit is operative to control flow of second current through a combination of the first substrate and the second inductor (Chen figs 1,2, and 45, terminal node of the first inductor corresponds to the output phase connection that directly bridges the active switching devices with the inductor windings; fig. 1, 22 DrMOS layer is disposed between a portion of the first substrate PCB2 14 and the Coupled Inductor 16; In the Schematic fig. 45, the 4-Phase Buck Unit, the nodes directly connecting the switching power stages (half-bridges formed by high-side FETs QH1-H4 and low-side FETs QL1-L4 to the respective phase inductors (L1, L2, L4, etc.) serve as these terminal nodes. Therefore, the terminal node is the switching node output (phase node) of the DrMOS / GaN power stage that feeds current into a distinct winding phase of the coupled inductor stack. DrMOS/GaN half-bridges directly control the flow of the first current through its phase winding of the coupled inductor. The multi-layer routing configuration through the first substrate PCB2 14 allows parallel multi-phase stages (such as the separate 2:1 Switched-Capacitor and 4-Phase Buck branches shown in FIG. 45) to collectively regulate current through a combination of the substrate layers and the adjacent inductor components).
Regarding claim 35, Chen and Cho disclose a multi-phase power converter in claim 1, wherein a terminal node of the first inductor is directly connected to a first portion of the first power stage circuit, the first portion of the first power stage circuit disposed between a first portion of the first substrate and the first inductor (Chen fig 1, DrMOS 22 is sandwiched between the first substrate PCB2 14 and the Coupled Inductor 16 therefore, the terminal nodes of the inductor connect directly downward into these power components); wherein the first power stage circuit is operative to control flow of first current through the first inductor (Chen fig 45, high-side MOSFETs QH1- QH4 and low-side MOSFETs QL1-QL4 drive individual inductor phases L1-L4 which explicitly teaches power stage switches QH/QL operating to control phase currents (each marked at 25A, summing up to 100A) through their respective inductors); and wherein the second power stage circuit is operative to control flow of second current through a combination of the first substrate and the second inductor (Chen fig. 45 shows multiple identical multi-phase converter blocks stacked or running in parallel to achieve a total output current 300A combined. In a multi-substrate vertical stack like the one shown in FIG. 1 and FIG. 2, the parallel currents from the distinct vertical layers/stages must route through the vertical interconnects (vias/pins) and planes embedded within the substrate board PCB2 14 to combine at the load CPU/TPU 18 on PCB1. Therefore, the second power stage controls a separate current path that utilizes the physical conductive layers/vias of the first substrate to join the shared power network).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US20230137975A1) and Cho (US9515014 B2) as applied to claim 1 above, and further in view of Hsiao et al. (US20140022737A1), hereinafter Hsiao.
Regarding claim 9, Chen and Cho disclose the multi-phase power converter as in claim 1.
Chen does not disclose a third substrate extending along a third substrate plane, wherein said third substrate plane is substantially perpendicular to the first substrate plane.
Hsiao discloses a power system with multiple substrates horizontal and a vertical substrate that is perpendicular to the multiple horizontal substrates . Hsiao discloses a third substrate extending along a third substrate plane, wherein said third substrate plane is substantially perpendicular to the first substrate plane (figs 1 and 2, substrates 10 and 300 perpendicular to substrate 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen and incorporate a third substrate perpendicular to two horizontal substrates as taught by Hsiao. The advantage of this design is to place additional components on the vertical substrate that is perpendicular to the horizontal substate to offer a space saving solution.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US20230137975A1) and Cho (US9515014 B2) as applied to claim 1 above, and further in view of Leong et al. (US20210118601A1), hereinafter Leong.
Regarding claim 13, Chen and Cho disclose the multi-phase power converter as in claim 1 with inductors (Chen fig 2, 16).
Cheng does not disclose wherein the first inductor comprises a first non-winding electrically conductive path, wherein the second inductor comprises a second non-winding electrically conductive path, and wherein an axis of the first non-winding electrically conductive path and an axis of the second non-winding electrically conductive path are substantially parallel; and wherein the axis of the first non-winding electrically conductive path is disposed substantially perpendicular to the first substrate plane..
Leong discloses inductor devices in stacked power supply topologies. Leong discloses the first inductor (fig 1, 110 detailed version of each inductor device; also see fig 13 multi-phase power supply inductor section 110) comprises a first non-winding electrically conductive path (par [0027] “each of the one or more electrically conductive paths (such as pillars, rods, curved surfaces, etc.) through the core material of the inductor device follows a respective non-winding path from the first end of the inductor device to the second end of the inductor device”), wherein the second inductor (fig 1, 110 detailed version of each inductor device; also see fig 13 multi-phase power supply inductor section 110 with multiple inductors) comprises a second non-winding electrically conductive path (par [0027]), and wherein an axis of the first non-winding electrically conductive path and an axis of the second non-winding electrically conductive path are substantially parallel (par [0302] “each non-winding electrically conductive path (such as straight, axial, or direct path) in the inductor device 110, embodiments herein also include connecting multiple inductive paths in parallel to control a magnitude of inductance provided by the respective inductor device 110”); and wherein the axis of the first non-winding electrically conductive path is disposed substantially perpendicular to the first substrate plane(Leong fig 13, substrate 1205 is to the inductor devices which are described in par [0110] as having an input axial end 141 and an output axial end 142 that appear vertical if fig 13 compared to the horizontal substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen and incorporate the use of non-winding inductors connected in parallel as taught by Leong. The advantage of this design is to control inductance.
Allowable Subject Matter
Claim 32 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 32, Chen and Cho disclose the multi-phase power converter as in claim 3.
Chen and Cho fail to disclose further comprising: a first planar component fabricated from metal; a second planar component fabricated from metal; and wherein a combination of the first inductor, second inductor, and the first power converter circuitry is disposed between the first planar component in the second planar component.
Ge et al. (US 20250393130 A1) and Ji et al. (US 20200220474 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “a first planar component fabricated from metal; a second planar component fabricated from metal; and wherein a combination of the first inductor, second inductor, and the first power converter circuitry is disposed between the first planar component in the second planar component”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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