DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
5. Applicant’s election of Species II, Claims 1-20 in the reply filed on 11/11/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Upon further consideration of the elected species, it was found claims 16-20 pertain to non-elected Species III.
Claims 1-15 pertain to species I and II, which do not comprise of the placeholder structure of species III, claims 16-20.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/11/2025.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-6, 8-9, 11-12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su).
Su, Fig 29A: Cross-sections of integrated circuit structure
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Re Claim 1, (Currently Amended) Su teaches a semiconductor device comprising:
a channel structure (Epitaxial layers; 124; Fig 29A; ¶[0019]);
a 1st source/drain region (Source/drain epitaxial structures; 250S; Fig 29C; ¶[0049]) on the channel structure; and
an enlarged backside contact structure (Backside via rail/Source Contact; 152/352; Fig 29C; ¶¶[0035, 0074]) connected to the 1st source/drain region,
wherein the enlarged backside contact structure comprises a backside contact structure (Backside via rail; 152; Fig 29C; ¶[0035]) below the 1st source/drain region, a 1st side via structure (Source Contact on right side of 250S; 352; Fig 29C; ¶[0074]) at a 1st side (Left or ride side of 250S; Fig 29C) of the 1st source/drain region, and a 1st front contact structure (Source Contact above of 250S; 352; Fig 29C; ¶[0074]) at a 1st side (Left or ride side of 250S; Fig 29C) above the 1st source/drain region, and
wherein the backside contact structure is connected (152 is connected to 352; Fig 29C) to the 1st side via structure, which is connected to the 1st front contact structure.
Re Claim 2, (Currently Amended) Su teaches the semiconductor device of claim 1, further comprising:
a 2nd source/drain region (Source/drain epitaxial structures; 250D; Fig 29C; ¶[0049]) on the channel structure (Epitaxial layers; 124; Fig 35A; ¶[0019]); and
a 2nd front contact structure (Source/drain contact; 354; Fig 29C; ¶[0074]) connected to the 2nd source/drain region, above (354 is above 250D; Fig 29C) the 2nd source/drain region.
Re Claim 3, (Currently Amended) Su teaches the semiconductor device of claim 2, wherein a shape (Shape of 250S; Fig 29A) of the 1st source/drain region (Source/drain epitaxial structures; 250S; Fig 29C; ¶[0049]) is different (Shapes of 250S/250D are different per Fig 29A, i.e. 250D is a half-shape cut from 250S) from a shape (Shape of 250D; Fig 29A) of the 2nd source/drain region (Source/drain epitaxial structures; 250D; Fig 29A; ¶[0049]).
Re Claim 4, (Currently Amended) Su teaches the semiconductor device of claim 1, wherein the backside contact structure (Backside via rail; 152; Fig 29C; ¶[0035]) is connected to a bottom surface (backside rail 152 connects to contact 352 and semiconductor layer 115 creating a path to the bottom surface of 250S; Fig 29C) of the 1st source/drain region (Source/drain epitaxial structures; 250S; Fig 29C; ¶[0049]), the 1st side via structure (Source Contact on right side of 250S; 352; Fig 29C; ¶[0074]) is connected to a 1st side surface (Left or ride side of 250S; Fig 29C) of the 1st source/drain region, and the 1st front contact structure (Source Contact above of 250S; 352; Fig 29C; ¶[0074]) is connected to a top surface of the 1st source/drain region.
Re Claim 5, (Original) Su teaches the semiconductor device of claim 2, further comprising a buffer layer (Liner layer; 140; Fig 29C; ¶[0028]) between the 1st source/drain region (Source/drain epitaxial structures; 250S; Fig 29C; ¶[0049]) and the backside contact structure (Backside via rail; 152; Fig 29C; ¶[0035]),
wherein the 1st source/drain region comprises a different material component from that of the buffer layer (Source/drain region comprises Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP and liner layer comprises SiO2, SiN, SiCN, SiOC, SiOCN, the like, or combinations thereof; ¶¶[0028,0050]).
Re Claim 6, (Original) Su teaches the semiconductor device of claim 5, wherein the 1st source/drain region (Source/drain epitaxial structures; 250S; Fig 29C; ¶[0049]) comprises silicon germanium (SiGe) (Source/drain 250S may comprise SiGe; ¶[0050]) and the buffer layer comprises silicon (Si) (Liner layer 140 may comprise Si; ¶[0028]).
Re Claim 8, (Currently Amended) Su teaches the semiconductor device of claim 1, wherein the enlarged backside contact structure (Backside via rail/Source Contact; 152/352; Fig 29C; ¶¶[0035, 0074]) further comprises a 2nd side via structure (Source Contact on left side of 250S; 352; Fig 29C; ¶[0074]) at a 2nd side, opposite to the 1st side, of the 1st source/drain region (Source/drain epitaxial structures; 250S; Fig 29C; ¶[0049]),
wherein the 1st side via structure is connected to a 1st side surface (Right side surface of 250S; Fig 29C) of the 1st source/drain region, and
wherein the 2nd side via structure is connected to a 2nd side surface (Left side surface of 250S; Fig 29C), opposite to the 1st side surface, of the 1st source/drain region.
Re Claim 9, (Original) Su teaches the semiconductor device of claim 8, wherein the 2nd side via structure (Source Contact on left side of 250S; 352; Fig 29C; ¶[0074]) is connected to the 1st front contact structure (Source Contact above of 250S; 352; Fig 29C; ¶[0074]) and the backside contact structure (Backside via rail; 152; Fig 29C; ¶[0035]).
Re Claim 11, (Currently Amended) Su teaches a semiconductor device comprising:
a channel structure (Epitaxial layers; 124; Fig 35A; ¶[0019]);
a 1st source/drain region (Source/drain epitaxial structures/epitaxial layer/metal silicide region; 250S/252/340; Fig 29C; ¶[0049]) on the channel structure; and
an enlarged backside contact structure (Backside via rail/Source Contact/Semiconductor layer; 152/352/115; Fig 29C; ¶¶[0035, 0074]) connected to the 1st source/drain region,
wherein the enlarged backside contact structure contacts (Semiconductor layer 115 contacts 252/250S; Fig 29C) at least a bottom surface (Bottom surface of 252/250S; Fig 29C) and a 1st side surface (Right side of 250S; Fig 29C) of the 1st source/drain region.
Re Claim 12, (Original) Su teaches the semiconductor device of claim 11, wherein the enlarged backside contact structure (Backside via rail/Source Contact/Semiconductor layer; 152/352/115; Fig 29C; ¶¶[0035, 0074]) further contacts a top surface (Top surface of 340; Fig 29C) of the 1st source/drain region (Source/drain epitaxial structures/epitaxial layer/metal silicide region; 250S/252/340; Fig 29C; ¶[0049]).
Re Claim 14, (Original) Su teaches the semiconductor device of claim 11, further comprising:
a 2nd source/drain region (Source/drain epitaxial structures; 250D; Figs 29A/29C; ¶[0049]) on the channel structure (Epitaxial layers; 124; Fig 35A; ¶[0019]); and
a 2nd front contact structure (Source/drain contact; 354; Fig 29C; ¶[0074]) connected to the 2nd source/drain region, above the 2nd source/drain region.
Re Claim 15, (Original) Su teaches the semiconductor device of claim 14, wherein a shape (Shape of 250S; Fig 29A) of the 1st source/drain region (Source/drain epitaxial structures; 250S; Fig 29C; ¶[0049]) is different(Shapes of 250S/250D are different per Fig 29A, i.e. 250D is a half-shape cut from 250S) from a shape (Shape of 250D; Fig 29A) of the 2nd source/drain region (Source/drain epitaxial structures; 250D; Fig 29A; ¶[0049]).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) as applied to claims 4 and 9 above, and further in view of Yu, Li-Zhen et al. (Pub No. US 20210407900 A1) (hereinafter, Yu).
Re Claim 7, (Currently Amended) Su does not teach the semiconductor device of claim 4, wherein the 1st side surface of the 1st source/drain region is vertically plane.
In the same field of endeavor, Yu teaches the semiconductor device of claim 4, wherein the 1st side surface (Inner side surface of right side of epitaxial semiconductor material 54; Fig 29D) of the 1st source/drain region (Epitaxial semiconductor material; 54; Fig 29D; ¶[0119]) is vertically plane (Flat along the vertical axis; Fig 29D).
Yu, Fig 29D: MOSFET with enlarged backside contact structure
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a 1st side surface of the 1st source/drain region which is vertically plane, as taught by Yu, with the semiconductor device as taught by Su. One would have been motivated to do this with a reasonable expectation of success because the the corner effect is reduced, i.e. the intense electric fields and electron concentration around sharp corners between the source/drain region and gate/channels is eliminated, leading to lower fluctuations in potential threshold voltages and less leakage current.
Re Claim 10, (Original) Su does not teach the semiconductor device of claim 9, wherein the 2nd side surface of the 1st source/drain region is vertically plane.
In the same field of endeavor, Yu teaches the semiconductor device of claim 9, wherein the 2nd side surface (Inner side surface of left side of epitaxial semiconductor material 54; Fig 29D) of the 1st source/drain region (Epitaxial semiconductor material; 54; Fig 29D; ¶[0119]) is vertically plane (Flat along the vertical axis; Fig 29D).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a 2nd side surface of the 1st source/drain region which is vertically plane, as taught by Yu, with the semiconductor device as taught by Su. One would have been motivated to do this with a reasonable expectation of success because the the corner effect is reduced, i.e. the intense electric fields and electron concentration around sharp corners between the source/drain region and gate/channels is eliminated, leading to lower fluctuations in potential threshold voltages and less leakage current.
10. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) as applied to claim 12 above, and further in view of Yu, Li-Zhen et al. (Pub No. US 20210407900 A1) (hereinafter, Yu).
Re Claim 13, (Original) Su does not teach the semiconductor device of claim 12, wherein the enlarged backside contact structure contacts a 2nd side surface, opposite to the 1st side surface, of the 1st source/drain region.
In the same field of endeavor, Yu teaches the semiconductor device of claim 12, wherein the enlarged backside contact structure (Backside via structure/Metal silicide portion; 120/173; Fig 29D; ¶[0137]) contacts a 2nd side surface (Inner side surface of left side of epitaxial semiconductor material 54; Fig 29D), opposite to the 1st side surface (Inner side surface of right side of epitaxial semiconductor material 54; Fig 29D), of the 1st source/drain region (Epitaxial semiconductor material; 54; Fig 29D; ¶[0119]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the enlarged backside contact structure contacts a 2nd side surface, opposite to the 1st side surface, of the 1st source/drain region, as taught by Yu, with the semiconductor device as taught by Su. One would have been motivated to do this with a reasonable expectation of success because the enlarged backside contact structure contacting the 2nd side surface allows for higher density wiring and low resistance between the connection via structures and backside metal interconnect structures (Yu, ¶¶[0001, 0093]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Huang, Yu-Xuan et al. (Pub No. US 20210202385 A1) discloses the present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.
[2] Yu, Li-Zhen et al. (Pub No. US 20210408274 A1) a semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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