DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 8, and 17-20 are rejected under 35 U.S.C. 102 as being anticipated by Sakai et. al. (US 2014/0315504 A1).
Regarding claims 1, 8 and 18, SAKAI teaches a voltage supply circuit (Fig. 12) for setting an amplifier supply voltage (VOUT, shown in Fig. 12 below as available at the terminal OUT) for an amplifier (1, as exemplarily shown in Figs. 2A and 4), the voltage supply circuit comprising:
a switch circuit (switching circuit 14 and reference voltage source 23 acting as a switching circuit in the voltage supply circuit of Fig. 12) for switchably coupling a supply terminal (VT) of the power amplifier (1, as shown below) between a first supply voltage (V1=low frequency linear amplifier voltage, tracking the envelop of the RF output of the amplifier + fixed DC-DC converter output voltage, §0037, Figs. 10A-10D, §0054-§0056, Fig. 11, §0059, Fig. 12, §0062-§0065) and a second supply voltage (V2=fixed DC-DC converter output voltage, §0038, Figs. 8A-8D, §0051-§0053, Fig. 11, §0059, Fig. 12, §0066-§0069), wherein a magnitude of the first supply voltage is greater than a magnitude of the second supply voltage (V1>V2), the switch circuit comprising:
a first transistor (inherently there are a plurality of transistors in the reference voltage source circuit 23 because there are switches, gates and current sources in this circuit) arranged to switchably couple a first supply voltage (V1) to a supply terminal (VOUT) of the amplifier (1); and
a second transistor (inherently there are a plurality of transistors in the switching circuit 14 because there are switches and inverter in this circuit) arranged to switchably couple (the switching circuit 14 selects the signal Ampref and inputs it to the Amp 12) a second supply voltage (V2) to the supply terminal (VOUT) of the amplifier (1), wherein a magnitude of the first supply voltage (V1) is greater than a magnitude of the second supply voltage (V2); and
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Fig. 12 of Sakai showing the amplifier (1) of Fig. 1 and annotated by the examiner for ease of reference.
Wherein, per claim 8, the first transistor and the second transistor are arranged in an anti-series configuration (the transistors as perceived in the reference voltage source circuit 23 and the switching circuit 14 are in different paths stemming from output voltage sensor 21 and as such they are in anti-series1 configuration because they have one common node (i.e., voltage sensor 21) but moving in two different directions,);
Further per claim 18, the first transistor (one or more of the transistors as perceived in the switches of the reference voltage source circuit 23) arranged to switchably couple a first supply voltage (V1) to a supply terminal (VT) of the amplifier (1);
a second transistor (one or more of the transistors as perceived in the switching circuit 14) arranged to switchably couple a second supply voltage (V2) to the supply terminal (VT) of the power amplifier (1), and
a control circuit (2) configured to control the switch circuit (buffer circuit, 14, 21, 23 and 24) to set an amplifier supply voltage at the supply terminal (VOUT) of the amplifier (1, Fig. 2A and Fig. 4) based on an output signal (§0075) of the amplifier (1, Fig. 2A and Fig. 4),
wherein the control circuit (2) is configured to set2 (§0052-§0056) the amplifier supply voltage (VOUT) to substantially equal the second supply voltage (V2) when a magnitude of a tracking voltage (envelope tracking sensed by the output voltage sensor 21) is less than the magnitude of the second supply voltage (V2) and set (§0044-§0051) the amplifier supply voltage to track the amplifier output signal (in envelope tracking mode) when the magnitude of the tracking voltage (sensed by the output voltage sensor 21) is greater than the magnitude of the second supply voltage (V2), and
wherein the tracking voltage (envelope tracking, §0056) is based on the output signal of the amplifier (following the peaks and troughs of the RF signal, §0023).
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Fig. 3A (top) and Fig. 3B (bottom) of Sakai annotated by the examiner.
wherein per claim 2, the magnitude of the tracking voltage (exemplarily shown in Fig. 3A as ENVELOPE OF PA TRANSMISSION SIGNAL and in Fig. 3B, so long as the right bar (2) remains below the left bar (1), annotated by the examiner) is less than the magnitude of the second supply voltage (V2, exemplarily shown in Fig. 3A as fixed power supply voltage, §0035), turn off the first transistor (one or more of the transistors as perceived in the switches of the reference voltage source circuit 23, Fig. 12, §0066-§0069) and turn on the second transistor (one or more of the transistors as perceived in the switching circuit 14, Fig. 12, §0066-§0069), and
when the magnitude of the tracking voltage (exemplarily shown in Fig. 3B, when the right bar (2) moves above the left bar (1), annotated by the examiner) is greater than the magnitude of the second supply voltage (V2), turn on the first transistor (one or more of the transistors as perceived in the switches of the reference voltage source circuit 23, Fig. 12, §0062-§0065) and turn off the second transistor (one or more of the transistors as perceived in the switching circuit 14, Fig. 12, §0062-§0065); and
wherein per claims 4, 17 and 20, the tracking voltage is equal to an output voltage of the amplifier plus a headroom voltage (see Fig. 3A).
wherein per claim 19, the control circuit is configured, when the magnitude of the tracking voltage is greater than the magnitude of the second supply voltage (up to the threshold, §0035), to turn on the first transistor (one or more of the transistors as perceived in the switches of the reference voltage source circuit 23, Fig. 12, §0066-§0069) by an amount necessary (to add the linear amplifier 12 output) to set the amplifier supply voltage to equal the tracking voltage (VOUT, Fig. 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai in view of Chin Hsia, “Integrated Current Detector for High Voltage Power Switches using LDMOS Transistors”, 2016 International Symposium on Computer, Consumer and Control, IEEE Computer Society.
Regarding Claim 16, Sakai teaches all limitations of claim 8 and Sakai further teaches that the power supply is an integrated circuit (IC). It is inherent that in order to integrate comparators, logic gates and switches as the power supply (10) and the control circuit 2 are comprising of plurality of transistors used as switches in the semiconducting IC and most often these are Silicon MOSFET transistors.
Hsia teaches use of LDMOS transistors in similar filed of endeavor of Integrated Current Detector for High Voltage Power Switches because High voltage lateral double-diffusion MOS (LDMOS) transistors can work in high speed and high voltage scenario due to their characteristics to provide a low Ron resistance at a given breakdown voltage.
Therefore, a person of ordinary skill in the art before the filing of the current invention would find it obvious to implement LDMOS transistors as High Voltage Power Switches of Sakai for the benefit of speed and low loss over its regular MOSFET counterparts.
Allowable Subject Matter
Claims 3, 5-7, 9-15 are objected to as being dependent upon a rejected base claims 2 and 8 respectively but would be allowable if rewritten in independent form including all the limitations of the base claims 2 and 8 and any intervening claims.
Claims 3, 5 and 11-15 are allowable because the closest prior art of record, Sakai teaches operational amplifiers for comparing the tracking voltage against threshold, however the first and second transistors’ operation is not explicitly matches with claims 3, 5 or 11-15 of the current invention.
Claims 6, 7 and 9, are allowable because the closest prior art of record JANG although teaches that the first transistor and the second transistor are both n-type transistors (the first switch SW1 is an n-type or p-type transistor, §0079 and the second switch SW2 is an n-type or p-type transistor, §0085), and wherein a drain terminal of the first transistor (211) is coupled to the first supply voltage (VCC1), and a source terminal of the first transistor is coupled to the supply terminal (T_VCC), of the amplifier (300) or vice versa for the p-type transistor, and contrary to claim 6, a drain terminal of the second transistor (212) is coupled to the second supply voltage supply (VCC2) and a source terminal of the second transistor is coupled to the supply terminal (T_VCC) of the amplifier (300) or vice versa for the p-type transistor, not the anti-series connection as claimed.
Claim 10 is allowable over the closest prior art of record Sakai or Jang because neither of the closest prior arts teaches the reverse biasing of the body diode of the transistors as claimed.
Conclusion
The prior art Jang et. al. (US 2023/0109988 A1) made of record and not relied upon is considered pertinent to applicant's disclosure.
Jang teaches a circuit (20C) for setting an amplifier supply voltage (VT) for an amplifier (PA, 300), with switches (SW1, SW2) comprising a first transistor (211) and a second transistor (212) to switchably couple a first supply voltage (VCC1) and a second supply voltage (VCC2) respectively to a supply terminal (VT) of the amplifier (PA, 300); However, it is not apparent, that VCC1 > VCC2; and
Jang teaches a control circuit (230, 221, 222) to set an amplifier supply voltage based on an input signal contrary to output signal as claimed.
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Fig. 7 of Jang reproduced for ease of reference.
Although the control circuit is configured to set the amplifier supply voltage (VT) to second supply voltage (VCC2) or a first supply voltage (VCC1) based on input signal modulation type instead of a tracking voltage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 See Fig. 195 of Balanced CE and CS stages — Structured Electronics Design.
2 Please referred to Figs. 7-12 to understand that in accordance with the amplifier operation control
signal, the Amp 12 changes the operation mode between a variable voltage mode (V1= low frequency linear amplifier (12) voltage, tracking the envelop of the RF output of the amplifier + fixed DC-DC converter (11) output voltage, §0044-§0051) and a fixed voltage mode (fixed DC-DC converter (11) output voltage, §0052-§0056).