Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 6, 10, 12, 13, and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 20220037382 A1), in view of Dabral (US 11158607 B2).
Regarding independent claim 1, Komai teaches a three-dimensional (3D) stack comprising: a first semiconductor wafer comprising a plurality of first die sites, wherein the plurality of first die sites comprises at least first functional die sites; a second semiconductor wafer stacked above the first semiconductor wafer and comprising a plurality of second die sites (Fig. 1, W1, W2; [0114], "FIG. 1 schematically represents WoW in which a wafer W1 having plural solid-state image pickup elements 11 formed thereon, a wafer W2 having plural memory circuits 12 formed thereon, and a wafer W3 having plural logic circuits 13 formed thereon are joined and stacked in a state in which the wafer W1, the wafer W2, and the wafer W3 are finely aligned."), wherein plurality of second die sites comprises second functional die sites and second non-functional die sites (Fig. 1; [0122], "In addition, in FIG. 1, configurations that are in the solid-state image pickup elements 11, the memory circuits 12, and the logic circuits 13 formed on the wafers W1 to W3, and are to be bad elements are represented by colored squares."); and a first redistribution layer located between the first semiconductor wafer and the second semiconductor wafer (Fig. 9, 120, 122, 121; [0163], "With such a configuration, the inter-circuit connection between the solid-state image pickup element 120, and the memory circuit 121 and the logic circuit 122 can be formed by forming terminals at a wire density of very thin wires by the semiconductor lithography technology as in WoW.").
However, Komai does not teach wherein the first redistribution layer electrically connects the first functional die sites of the first semiconductor wafer to the second functional die sites of the second semiconductor wafer and by-passes the second non-functional die sites of the second semiconductor wafer.
However, in the same field of endeavor, Dabral teaches wherein the first redistribution layer electrically connects the first functional die sites of the first semiconductor wafer to the second functional die sites of the second semiconductor wafer and by-passes the second non-functional die sites of the second semiconductor wafer (Fig. 4, 312; (Col. 8, Lines 31-34), "Accordingly, via 312 connections may be etched and formed into the die-level BEOL build-up structure 115 layers to connect with the die-level BEOL layers, while bypassing the testing pads 112.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack of Komai with the bypassing of non-functional dies of Dabral so as to "avoid…the test pads [non-functional dies]", (Dabral, Col. 9, Lines 30-31).
Regarding dependent claim 3, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches the first redistribution layer is in direct contact with a backside of the first semiconductor wafer and is electrically connected to a frontside of the second semiconductor wafer via a plurality of interconnects (Fig. 5, 133; [0156], "As depicted in FIG. 10, along a junction surface F1 on which the solid-state image pickup element 120 and the memory circuit 121 face each other, pads 120b and 121b electrically connected with the wires 120a and 121a, respectively, are mutually CuCu-joined.").
Regarding dependent claim 5, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 3, and further teaches wherein the plurality of interconnects comprises solder balls, metal bond pads or a combination thereof (Fig. 10; 120b, 121b; [0172], "As depicted in FIG. 10, along a junction surface F1 on which the solid-state image pickup element 120 and the memory circuit 121 face each other, pads 120b and 121b electrically connected with the wires 120a and 121a, respectively, are mutually CuCu-joined.").
Regarding dependent claim 6, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches wherein a frontside of the first semiconductor wafer is electrically connected to the first redistribution layer located on a backside of the second semiconductor wafer (Fig. 5, 133; [0156], "As depicted in FIG. 10, along a junction surface F1 on which the solid-state image pickup element 120 and the memory circuit 121 face each other, pads 120b and 121b electrically connected with the wires 120a and 121a, respectively, are mutually CuCu-joined.").
Regarding dependent claim 10, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches wherein the first redistribution layer is customized to include electrically conductive wires that electrically connect the first functional die sites of the first semiconductor wafer to the second functional die sites of the second semiconductor wafer (Fig. 10, 120a, 121a; [0172], "As depicted in FIG. 10, along a junction surface F1 on which the solid-state image pickup element 120 and the memory circuit 121 face each other, pads 120b and 121b electrically connected with the wires 120a and 121a, respectively, are mutually CuCu-joined."), and Dabral further teaches and that bypasses the second non-functional die sites of the second semiconductor wafer (Fig. 4, 312; (Col. 8, Lines 31-34), "Accordingly, via 312 connections may be etched and formed into the die-level BEOL build-up structure 115 layers to connect with the die-level BEOL layers, while bypassing the testing pads 112.").
Regarding dependent claim 12, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches wherein the first functional die sites and the second functional die sites comprise active circuits (Fig. 1, 12, 13; [0116], "A solid-state image pickup apparatus 1 in FIG. 2 includes on-chip lenses and on-chip color filters 10, a solid-state image pickup element 11, a memory circuit 12, a logic circuit 13, and a support board 14 that are stacked in this order from above.").
Regarding dependent claim 13, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches wherein the second non-functional dies comprise at least a partially inactive active circuit ([0164], "In addition, only those confirmed to be good chips are connected as the memory circuit 121 and the logic circuit 122. Accordingly, bad chips of each wafer, which is a drawback of WoW, decrease, and so the occurrence of yield loss can be reduced.").
Regarding dependent claim 15, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches wherein the 3D stack is a wafer stack (Fig. 1, W1, W2; [0114], "FIG. 1 schematically represents WoW in which a wafer W1 having plural solid-state image pickup elements 11 formed thereon, a wafer W2 having plural memory circuits 12 formed thereon, and a wafer W3 having plural logic circuits 13 formed thereon are joined and stacked in a state in which the wafer W1, the wafer W2, and the wafer W3 are finely aligned.").
Regarding dependent claim 16, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches wherein the first redistribution layer comprises an interconnect structure that contains electrically conductive wires embedded in an interconnect dielectric layer (Fig. 5, 133; [0156], "As depicted in FIG. 10, along a junction surface F1 on which the solid-state image pickup element 120 and the memory circuit 121 face each other, pads 120b and 121b electrically connected with the wires 120a and 121a, respectively, are mutually CuCu-joined.").
Regarding dependent claim 17, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1. Dabral further teaches wherein the first redistribution layer has different patterns for electrically connecting the first functional die sites of the first semiconductor wafer to the second functional die sites of the second semiconductor wafer and for by-passing the second non-functional die sites of the second semiconductor wafer (Fig. 4, 312; (Col. 8, Lines 31-34), "Accordingly, via 312 connections may be etched and formed into the die-level BEOL build-up structure 115 layers to connect with the die-level BEOL layers, while bypassing the testing pads 112.").
Regarding dependent claim 18, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1, and further teaches further comprising: a third semiconductor wafer stacked above the second semiconductor wafer and comprising a plurality of third die sites, wherein plurality of third die sites comprises third functional die sites (Fig. 1, W1, W2, W3; [0114], "FIG. 1 schematically represents WoW in which a wafer W1 having plural solid-state image pickup elements 11 formed thereon, a wafer W2 having plural memory circuits 12 formed thereon, and a wafer W3 having plural logic circuits 13 formed thereon are joined and stacked in a state in which the wafer W1, the wafer W2, and the wafer W3 are finely aligned."); and a second redistribution layer located between the second semiconductor wafer and the third semiconductor wafer, wherein the second redistribution layer electrically connects the second functional die sites of the second semiconductor wafer to the third functional die sites of the third semiconductor wafer (Fig. 2, 21-1, 21-2; [0117], "Here, by applying the WoW technology, wires 21-1 that electrically connect the solid-state image pickup element 11 and the memory circuit 12, and wires 21-2 that electrically connect the memory circuit 12 and the logic circuit 13 can form connections at fine pitches.").
Claim(s) 2 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 20220037382 A1), in view of Dabral (US 11158607 B2) and Kim (US 10431565 B1).
Regarding dependent claim 2, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1. However, as previously combined, they do not teach further comprising at least one second partially functional die site on the second semiconductor wafer, wherein the first redistribution layer further connects the fully functional die sites of the first semiconductor wafer to the at least one partially functional die sites on the second semiconductor wafer.
However, in the same field of endeavor, Kim teaches further comprising at least one second partially functional die site on the second semiconductor wafer, wherein the first redistribution layer further connects the fully functional die sites of the first semiconductor wafer to the at least one partially functional die sites on the second semiconductor wafer (Fig. 6, 104; (Col. 6, Lines 59-63), "At least one or more of the conductive bond pads 108 electrically coupled by interconnect wiring 220 to the partial solid state circuitry 222 formed in the substrate 206 generally reside in the region 226 laterally outward of the inductor 202.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai and Dabral with the partially functional die sites of Kim so that "improved wafer bonding yield and process window is enhanced without compromising the gross number of dies per wafer that can be realized from a stacked wafer assembly", (Kim, Col. 4, Lines 2-5).
Regarding dependent claim 11, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 10. However, as previously combined, they do not teach wherein the electrically conductive wires present in the first redistribution layer connect at least one signal line, at least one power line and at least one ground line that is present in the first semiconductor wafer and to interconnects that are present on a frontside of the second semiconductor wafer.
However, in the same field of endeavor, Kim teaches wherein the electrically conductive wires present in the first redistribution layer connect at least one signal line, at least one power line and at least one ground line that is present in the first semiconductor wafer and to interconnects that are present on a frontside of the second semiconductor wafer (Fig. 2, 212; (Col. 5, Lines 49-55), "The bond pads 108 are conductive terminations of circuitry 212 with the full die 106 that provide one of ground, power or data communications. The conductive bond pads 108 may optionally include solder bumps (not shown) to facilitate ground, power and signal transmission with the die on the second wafer, as further discussed below.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai and Dabral with the conductive wires of Kim so as to be "configured as a programmable logic device", (Kim, Col. 5, Lines 17-18).
Claim(s) 4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 20220037382 A1), in view of Dabral (US 11158607 B2) and Yu (US 20120313247 A1).
Regarding dependent claim 4, Komai, as previously modified by Dabral, teaches the 3D stack of claim 1. However, as previously combined, they do not teach further comprising at least one signal line, at least one power line and at least one ground line present in each of the first semiconductor wafer and the second semiconductor wafer.
However, in the same field of endeavor, Yu teaches further comprising at least one signal line, at least one power line and at least one ground line present in each of the first semiconductor wafer and the second semiconductor wafer (Fig. 1, 111; [0018], "The through silicon via (TSV) openings 111 may be formed into the first side 102 of the semiconductor substrate 101.", [0001], "This expansion allows for, among other things, a three-dimensional stacking of semiconductor dies, with connections going through the through silicon vias and providing power, ground, and signal lines throughout the three-dimensional stack.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai and Dabral with the power, signal, and ground lines of Yu so as "to provide electrical connections to a backside of the semiconductor substrate'", (Yu, [0001]).
Regarding dependent claim 7, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1. However, as previously combined, they do not teach further comprising at least one signal line, at least one power line and at least one ground line present in each of the first semiconductor wafer and the second semiconductor wafer.
However, in the same field of endeavor, Yu teaches further comprising at least one signal line, at least one power line and at least one ground line present in each of the first semiconductor wafer and the second semiconductor wafer (Fig. 1, 111; [0018], "The through silicon via (TSV) openings 111 may be formed into the first side 102 of the semiconductor substrate 101.", [0001], "This expansion allows for, among other things, a three-dimensional stacking of semiconductor dies, with connections going through the through silicon vias and providing power, ground, and signal lines throughout the three-dimensional stack.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai and Dabral with the power, signal, and ground lines of Yu so as "to provide electrical connections to a backside of the semiconductor substrate'", (Yu, [0001]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 20220037382 A1), in view of Dabral (US 11158607 B2), Yu (US 20120313247 A1), and Brown (US 20220077112 A1).
Regarding dependent claim 8, Komai, as previously modified by Dabral and Yu, teaches the 3D stack of Claim 7. However, as previously combined, they do not teach wherein the at least one signal line is electrically isolated from an active circuit present in one of the first functional die sites and one of the second functional die sites.
However, in the same field of endeavor, Brown teaches wherein the at least one signal line is electrically isolated from an active circuit present in one of the first functional die sites and one of the second functional die sites (Fig. 3, 142; [0053], "Furthermore, the control system may determine that one or more TSVs 142 are faulty, and thus are to be bypassed…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai, Dabral, and Yu with the electrically isolated signal line of Brown so as to "to couple the first circuit to the second circuit if a fault is detected in the first TSV", (Brown, Abstract).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 20220037382 A1), in view of Dabral (US 11158607 B2), Yu (US 20120313247 A1), and Song (US 20210272893 A1).
Regarding dependent claim 9, Komai, as previously modified by Dabral and Yu, teaches the 3D stack of Claim 7. However, as previously combined, they do not teach wherein the at least one power line is not connected to an active circuit present in in one of the first functional die sites and one of the second functional die sites.
However, in the same field of endeavor, Song teaches wherein the at least one power line is not connected to an active circuit present in in one of the first functional die sites and one of the second functional die sites (Fig. 3A, VDD, AC2; [0053], "The first insulating structure IP1 may directly cover a top surface of the contact structure UC, which is composed of the first gate contact GC1 and the second active contact AC2. Due to the first insulating structure IP1, the power line VDD may not be in contact with the top surface of the contact structure UC. Thus, due to the first insulating structure IP1, the power line VDD may be disconnected from the contact structure UC.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai, Dabral, and Yu with the unconnected power line of Song so as to "provide electronic devices with fast speed and/or low power consumption", (song, [0003]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 20220037382 A1), in view of Dabral (US 11158607 B2) and Hsu (US 20200294965 A1).
Regarding dependent claim 14, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 1. However, as previously combined, they do not teach wherein the 3D stack is a chip stack.
However, in the same field of endeavor, Hsu teaches wherein the 3D stack is a chip stack ([0001], "...because of the decreased length of interconnects between the stacked chips.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai and Dabral with the chip stack of Hsu so as to "provide improved integration density and other advantages, such as faster speeds and higher bandwidth", (Hsu, [0001]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komai (US 20220037382 A1), in view of Dabral (US 11158607 B2) and Uzoh (US 20200411483 A1).
Regarding dependent claim 19, Komai, as previously modified by Dabral, teaches the 3D stack of Claim 18. However, as previously combined, they do not teach further comprising: a fourth semiconductor wafer stacked above the third semiconductor wafer and comprising a plurality of fourth die sites, wherein plurality of fourth die sites comprises fourth functional die sites and a non-functional die site; and a third redistribution layer located between the third semiconductor wafer and the fourth semiconductor wafer, wherein the third redistribution layer electrically connects the third functional die sites of the third semiconductor wafer to the fourth functional die sites of the fourth semiconductor wafer and by-passes the non-functional die site on the fourth semiconductor wafer.
However, in the same field of endeavor, Uzoh teaches a fourth semiconductor wafer stacked above the third semiconductor wafer and comprising a plurality of fourth die sites, wherein plurality of fourth die sites comprises fourth functional die sites and a non-functional die site (Fig. 17, 1704; [0084], "The stack of dies 102 is allowed to cool to the lower bonding temperature for additional processing if needed before attaching the top extra dummy die 1704 to the upper surface of the last die in the stack of dies 102."); and a third redistribution layer located between the third semiconductor wafer and the fourth semiconductor wafer ([0097], "...wherein the direct bonding occurs at the dielectric surfaces followed by direct bonding between metal bonding pads, vias, and interconnects of the dies…"), wherein the third redistribution layer electrically connects the third functional die sites of the third semiconductor wafer to the fourth functional die sites of the fourth semiconductor wafer and by-passes the non-functional die site on the fourth semiconductor wafer (Fig. 22, 2208; [0099], "Additionally, layer 2208 may also contain metal materials as conductive pads, wherein the direct bonding occurs at the dielectric surfaces followed by direct bonding between metal bonding pads, vias, and interconnects of the dies 2202 in an annealing step of the same overall direct bonding operation.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the 3D stack as described by the combination of Komai and Dabral with the fourth wafer of Uzoh "for increased reliability and improved yields in microelectronics", (Uzoh, [0005]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210327778 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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