DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/3/2025 have been fully considered but they are not persuasive.
Applicant argues that Horisaki fails to teach or suggest “wherein the first error correction operation determines a correction capability according to an error count, and the second error correction operation determines a correction capability according to the error count and an erasure count” because Fig. 6 as referenced in the Rejection merely discloses determining a correction mode 32 based on the size (byte) of the correctable code errors and the correctable code erasures.
While the Examiner does not dispute Applicant’s analysis, the Examiner asserts that the information shown in Fig. 6 necessarily teaches the above limitation. For each of the modes shown by Horisaki, a correction capability according to an error count is shown, as well as a corresponding erasure count. It can clearly be seen from Fig. 6 that the maximum error correction capability increases as the number of erasures increases. Therefore, a first correction capability can be determined in mode 0 without erasures, and another correction capability can be determined according to both error count and an erasure count such as in mode 4. This teaching is not unlike Applicant’s own teaching in Fig. 4B, which shows the same information.
Applicant further argues that the error correction history storing unit 14 of Horisaki does not disclose “wherein the failure information further comprises sub wordline failure information, sub wordline driver failure information, or on-die error correction history information” as stated in the Office Action on page 4 because Horisaki merely discloses the error correction history storing unit 14 that stores history of the address where the code error is detected based on the code error position data 25 that is input from the decoding unit 12, and the error correction history storing unit 14 outputs error history data 26 that indicates the history of the address to the erasure code setting unit 13.
The Examiner asserts that the error correction history storing unit 14 is on the chip 10, and may thus be considered “on-die error correction history information” as claimed.
Applicant finally argues that the erasure code setting unit 13 of Horisaki does not disclose, “wherein the erasure is determined based on the failure information” as stated in the Office Action on page 5 because Horisaki merely discloses the erasure code setting unit 13 that generates erasure information 27 based on the error history data 26.
The Examiner notes that if the erasure code setting unit 13 that generates erasure information 27 based on the error history data 26, then it is “based on the failure information” 26.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 4, 6, 7, 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Horisaki et al (US Pat. 8,176,389; hereinafter referred to as Horisaki) in view of Kubo (US Pat. Pub. 2013/0173972) in view of Eun et al (US Pat. Pub. 2010/0287447; hereinafter referred to as Eun).
As per claim 1: Horisaki teaches a method of operating a storage device, comprising:
performing a read operation on a memory device (col. 2, lines 56-60) to determine whether a correctable error has occurred in data stored in the memory device (col. 3, lines 21-24);
storing failure information associated with the correctable error in a buffer memory (Fig. 1, 14);
loading the failure information from the buffer memory (Fig. 1, 26; col. 3, lines 34-36); and
performing a second error correction operation on the read data by using the failure information (col. 3, lines 37-48),
wherein the failure information includes error correction code history information of a memory cell of the memory device (Fig. 1, 14; col. 3, lines 31-36),
wherein the first error correction operation determines a correction capability according to an error count (Fig. 6, correctable errors column), and the second error correction operation determines a correction capability according to the error count and an erasure count (Fig. 6, correctable code erasures column),
wherein an erasure is determined based on the failure information (Fig. 1, 13; Figs. 4), and
wherein the failure information further comprises sub wordline failure information, sub wordline driver failure information, or on-die error correction history information (Fig. 1, 14).
Not explicitly disclosed is periodically performing a patrol read operation on the memory device. However, Kubo in an analogous art teaches periodically performing a patrol read operation on a memory device (paragraph 17). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to periodically perform a patrol read operation.
This modification would have been obvious for one of ordinary skill in the art at the time of filing because doing so would have identified failures and averted unrecoverable data loss without affected performance (paragraphs 17-18).
Also not explicitly disclosed is loading the failure information upon determining that an uncorrectable error has occurred as a result of a first error correction operation being performed on data read from the memory device. However, Eun in an analogous art teaches performing erasure decoding (Fig. 4, S130) upon determining that an uncorrectable error has occurred (Fig. 4, S120 No) as a result of a first error correction operation being performed on data read from a memory device (Fig. 4, S110).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to load the failure information 26 of Horisaki to perform erasure decoding upon determining that an uncorrectable error has occurred as taught by Eun in Fig. 4, S130. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Horisaki teaches that an uncorrectable error (Fig. 3B) may become correctable by enabling erasure decoding (Fig. 4B).
As per claim 3: Horisaki et al teach the method of claim 1. Not explicitly disclosed is wherein the buffer memory comprises at least one of a dynamic random access memory (DRAM), a static random access memory (SRAM), a NAND flash memory, or a serial NOR (SNOR) flash memory. However, Kubo in an analogous art teaches NAND flash memory (Fig. 3, 310) for storing data bits (paragraph 12).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a NAND flash memory as the buffer of Horisaki. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Horisaki states that the buffer is a memory (col. 5, lines 45-47), and Kubo provides an example of one suitable storage location.
As per claim 4: Horisaki further teaches the method of claim 1, wherein the first error correction operation and the second error correction operation have different correction capabilities from each other (Figs. 3b and 4b).
As per claim 6: Horisaki further teaches the method of claim 1, further comprising setting an error and erasure decoder mode to perform the second error correction operation (Fig. 1, 13).
As per claim 7: Horisaki further teaches the method of claim 1, further comprising reporting error information when an uncorrectable error has occurred as a result of the second error correction operation (col. 8, line 66-col. 9, line 6).
As per claim 10: Kubo further teaches the method of claim 1, wherein the storage device comprises a controller (Fig. 3, 320) configured to control at least one non-volatile memory device (Fig. 3, 310) and at least one volatile memory device (Fig. 3, 360), wherein the controller controls the memory device by using a memory manager (Fig. 3, 330).
As per claim 11:
Horisaki teaches a storage device, comprising:
at least one non-volatile memory device (col. 2, lines 56-60)
a memory device (Fig. 1, 20);
a buffer memory (Fig. 1, 14);
a controller configured to control the at least one non-volatile memory device (Fig. 1, 10), wherein the controller is configured to:
performing a read operation on a memory device (col. 2, lines 56-60) to determine whether a correctable error has occurred in data stored in the memory device (col. 3, lines 21-24);
store failure information associated with the correctable error in a buffer memory (Fig. 1, 14);
determine an erasure using the failure information from the buffer memory (Fig. 1, 27; col. 3, lines 34-40), wherein the controller performs a second error correction operation on the read data by using the determined erasure (col. 3, lines 37-48),
wherein the failure information includes error correction code history information of a memory cell of the memory device (Fig. 1, 14; col. 3, lines 31-36),
wherein the first error correction operation determines a correction capability according to an error count (Fig. 6, correctable errors column), and the second error correction operation determines a correction capability according to the error count and an erasure count (Fig. 6, correctable code erasures column),
wherein the failure information further comprises sub wordline failure information, sub wordline driver failure information, or on-die error correction history information (Fig. 1, 14).
Not explicitly disclosed is periodically performing a patrol read operation on the memory device. However, Kubo in an analogous art teaches periodically performing a patrol read operation on a memory device (paragraph 17). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to periodically perform a patrol read operation.
This modification would have been obvious for one of ordinary skill in the art at the time of filing because doing so would have identified failures and averted unrecoverable data loss without affected performance (paragraphs 17-18).
Also not explicitly disclosed is determining an erasure using the failure information upon determining that an uncorrectable error has occurred as a result of a first error correction operation being performed on data read from the memory device. However, Eun in an analogous art teaches performing erasure decoding (Fig. 4, S130) upon determining that an uncorrectable error has occurred (Fig. 4, S120 No) as a result of a first error correction operation being performed on data read from a memory device (Fig. 4, S110).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to load the failure information 26 of Horisaki to perform erasure decoding upon determining that an uncorrectable error has occurred as taught by Eun in Fig. 4, S130. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Horisaki teaches that an uncorrectable error (Fig. 3B) may become correctable by enabling erasure decoding (Fig. 4B).
As per claim 12: Kubo further teaches the storage device of claim 11, wherein the controller comprises a non-volatile memory controller (Fig. 3, 350) and a memory controller (Fig. 3, 320), wherein the non-volatile memory controller controls the at least one non-volatile memory device (Fig. 3, 310), and the memory controller controls the memory device (paragraph 13), wherein the memory controller performs the error correction operation on the read data (Fig. 3, 330, ECC).
As per claim 13: Horisaki further teaches the storage device of claim 11, wherein the controller further comprises the buffer memory configured to store the failure information (Fig. 1, 14).
As per claim 14: Kubo further teaches the storage device of claim 11, wherein the controller further comprises a processor configured to drive a memory manager (Fig. 3, 330) that controls the patrol read operation (paragraph 17).
As per claim 15: Horisaki further teaches the storage device of claim 11, wherein the wherein the controller sets an error and erasure decoder mode to perform the error correction operation (Fig. 1, 13) according to an internal policy or an external request (Fig. 1, 23 is an internal policy).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Horisaki in view of Kubo in view of Eun in view of Varanasi (US Pat. 10,120,753).
As per claim 8:
Horisaki et al teach the method of claim 1. Not explicitly disclosed is wherein each of the first error correction operation and the second error correction operation performs error correction using a Reed Solomon code. However, Varanasi in an analogous art teaches performing error correction on a memory using a Reed Solomon code (col. 3, lines 28-33).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a Reed Solomon code for the error correction operation of Horisaki. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it was one of a known type of error correction for use in memories, as shown by Varanasi in col. 3, lines 28-33.
Claim(s) 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Horisaki in view of Eun.
As per claim 16:
Horisaki teaches a method of operating a storage device, comprising:
performing a first error correction operation on read data of a memory device (col. 3, lines 21-24); and
performing a second error correction operation (col. 3, lines 37-48) by using failure information of the memory device (Fig. 1, 27),
wherein the first error correction operation determines a correction capability according to an error count (Fig. 6, correctable errors column), and the second error correction operation determines a correction capability according to the error count and an erasure count (Fig. 6, correctable code erasures column),
wherein an erasure is determined based on the failure information (Fig. 1, 13; Figs. 4), and
wherein the failure information further comprises sub wordline failure information, sub wordline driver failure information, or on-die error correction history information (Fig. 1, 14).
Not explicitly disclosed is performing the second error correction operation when an error of the read data is uncorrectable as determined by the first error correction operation. However, Eun in an analogous art teaches performing erasure decoding (Fig. 4, S130) upon determining that an uncorrectable error has occurred (Fig. 4, S120 No) as a result of a first error correction operation being performed on data read from a memory device (Fig. 4, S110).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to load the failure information 26 of Horisaki to perform erasure decoding upon determining that an uncorrectable error has occurred as taught by Eun in Fig. 4, S130. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Horisaki teaches that an uncorrectable error (Fig. 3B) may become correctable by enabling erasure decoding (Fig. 4B).
As per claim 17:
Horisaki teaches the method of claim 16, wherein the performing the first error correction operation comprises performing an error correction operation based on an error count (Fig. 6, correctable errors column).As per claim 20: Horisaki teaches the method of claim 16, further comprising collecting the failure information for the memory device (Fig. 1, 14).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 11-7.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111