Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 6, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20150255364 A1), in view of O'Brien (US 20220199799 A1).
Regarding independent claim 1, Gao teaches an integrated circuit structure ([0001], "The following description relates to integrated circuits ("ICs")."), comprising: and a plurality of metallization layers above the plurality of fin-based transistors (Fig. 1A, M1,2,3,4,5; [0026], "In this example, there are five levels of metallization, namely M1, M2, M3, M4, and M5; however, in other configurations there may be fewer or more levels of metallization."); a backside structure below the plurality of fin-based transistors; a carrier wafer or substrate bonded to the front side structure (Fig. 1A, 12; [0071], "For a signal via structure, there is a substrate 12-to-liner 15 interface 804…"); and a thermal conductive via that extends from a location at a bottom of or below the plurality of fin-based transistors to a location on or into the carrier wafer or substrate (Fig. 1A, 18, 21; [0071], "However, for a highly thermally conductive via conductor 21, thermal resistance thereof may be small enough in comparison to these other thermal resistances to be excluded from a thermal resistance determination.").
However, Gao does not teach a front side structure comprising: a device layer comprising a plurality of fin-based transistors.
However, in the same field of endeavor, O’Brien teaches a front side structure comprising: a device layer comprising a plurality of fin-based transistors (Fig. 6, 640; [0084], "The transistors 640 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include Fin-based transistors...").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure of Gao with the fin-based transistors of O’Brien for use "in the metal layers of a microprocessor device for analog circuitry, logic circuitry, or memory circuitry", (O'Brien, [0084]).
Regarding dependent claim 5, Gao, as previously modified by O’Brien, teaches the integrated circuit structure of claim 1, and further teaches wherein the thermal conductive via is electrically floating (Fig. 1A, 18; [0029], "...may be used to electrically isolate via structures 18 from substrate 12.").
Regarding independent claim 6, Gao teaches an integrated circuit structure ([0001], "The following description relates to integrated circuits ("ICs")."), comprising: and a plurality of metallization layers above the plurality of nanowire-based transistors (Fig. 1A, M1,2,3,4,5; [0026], "In this example, there are five levels of metallization, namely M1, M2, M3, M4, and M5; however, in other configurations there may be fewer or more levels of metallization."); a backside structure below the plurality of nanowire-based transistors; a carrier wafer or substrate bonded to the front side structure (Fig. 1A, 12; [0071], "For a signal via structure, there is a substrate 12-to-liner 15 interface 804…"); and a thermal conductive via that extends from a location at a bottom of or below the plurality of nanowire-based transistors to a location on or into the carrier wafer or substrate (Fig. 1A, 18, 21; [0071], "However, for a highly thermally conductive via conductor 21, thermal resistance thereof may be small enough in comparison to these other thermal resistances to be excluded from a thermal resistance determination.").
However, Gao does not teach a front side structure comprising: a device layer comprising a plurality of nanowire-based transistors.
However, in the same field of endeavor, O’Brien teaches a front side structure comprising: a device layer comprising a plurality of nanowire-based transistors (Fig. 6, 640; [0084], "The transistors 640 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include Fin-based transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure of Gao with the nanowire-based transistors of O’Brien for use "in the metal layers of a microprocessor device for analog circuitry, logic circuitry, or memory circuitry", (O'Brien, [0084]).
Regarding dependent claim 10, Gao, as previously modified by O’Brien, teaches the integrated circuit structure of claim 6, and further teaches wherein the thermal conductive via is electrically floating (Fig. 1A, 18; [0029], "...may be used to electrically isolate via structures 18 from substrate 12.").
Claim(s) 2-4 and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20150255364 A1), in view of O'Brien (US 20220199799 A1) and Shin (US 20220045010 A1).
Regarding dependent claim 2, Gao, as previously modified by O’Brien, teaches the integrated circuit structure of claim 1. However, as previously combined, they do not teach wherein the thermal conductive via comprises a dielectric liner and a conductive fill.
However, in the same field of endeavor, Shin teaches wherein the thermal conductive via comprises a dielectric liner and a conductive fill (Fig. 11, VST, SL, TP; [0076], "The thermal conductive via structure VST may further include a barrier/seed pattern SL…The barrier/seed pattern SL may also be interposed between the thermal conductive pad TP…", "The barrier/seed pattern SL may include a barrier layer and a seed layer that are sequentially stacked on each other. The barrier layer may include or may be formed of a metal nitride layer.", (Metal nitride is dielectric)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure as described by the combination of Gao and O’Brien with the liner and fill of Shin so that "heat generated from the first semiconductor apparatus CH1 may be transferred to the thermal radiation member HS (i.e., a heat sink)", (Shin, [0041]).
Regarding dependent claim 3, Gao, as previously modified by O’Brien and Shin, teaches the integr4ated circuit structure of claim 2. However, as previously combined, they do not teach wherein the conductive fill is selected from the group consisting of a copper fill, a tungsten fill, or a polysilicon fill.
However, Shin further teaches wherein the conductive fill is selected from the group consisting of a copper fill, a tungsten fill, or a polysilicon fill ([0043], "The thermal conductive pad TP and the second upper conductive patterns 34 may be the same in terms of thickness and material (e.g., metal such as copper).").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure as described by the combination of Gao, O’Brien, and Shin with the copper fill of Shin so that "thermal conductivity is high such that the thermal radiation member HS may serve as a heat sink of the semiconductor package", (Shin, [0034]).
Regarding dependent claim 4, Gao, as previously modified by O’Brien, teaches the integrated circuit structure of claim 1. However, as previously combined, they do not teach wherein the thermal conductive via does not electrically couple electrical features.
However, in the same field of endeavor, Shin teaches wherein the thermal conductive via does not electrically couple electrical features (Fig. 10, Fig. 11, VST; [0075], "The wiring structure 602 may include a thermal conductive layer TL, a thermal conductive pad TP, and a thermal conductive via structure VST that connects the thermal conductive layer TL to the thermal conductive pad TP.", (Only thermal parts are connected, no mention of connection to electrical parts)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure as described by the combination of Gao and O’Brien with the lack of electrical coupling of Shin for "allowing regulation of the temperature of the first semiconductor apparatus", (Shin, [0041]).
Regarding dependent claim 7, Gao, as previously modified by O’Brien, teaches the integrated circuit structure of claim 6. However, as previously combined, they do not teach wherein the thermal conductive via comprises a dielectric liner and a conductive fill.
However, in the same field of endeavor, Shin teaches wherein the thermal conductive via comprises a dielectric liner and a conductive fill (Fig. 11, VST, SL, TP; [0076], "The thermal conductive via structure VST may further include a barrier/seed pattern SL…The barrier/seed pattern SL may also be interposed between the thermal conductive pad TP…", "The barrier/seed pattern SL may include a barrier layer and a seed layer that are sequentially stacked on each other. The barrier layer may include or may be formed of a metal nitride layer.", (Metal nitride is dielectric)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure as described by the combination of Gao and O’Brien with the liner and fill of Shin so that "heat generated from the first semiconductor apparatus CH1 may be transferred to the thermal radiation member HS (i.e., a heat sink)", (Shin, [0041]).
Regarding dependent claim 8, Gao, as previously modified by O’Brien and Shin, teaches the integr4ated circuit structure of claim 7. However, as previously combined, they do not teach wherein the conductive fill is selected from the group consisting of a copper fill, a tungsten fill, or a polysilicon fill.
However, Shin further teaches wherein the conductive fill is selected from the group consisting of a copper fill, a tungsten fill, or a polysilicon fill ([0043], "The thermal conductive pad TP and the second upper conductive patterns 34 may be the same in terms of thickness and material (e.g., metal such as copper).").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure as described by the combination of Gao, O’Brien, and Shin with the copper fill of Shin so that "thermal conductivity is high such that the thermal radiation member HS may serve as a heat sink of the semiconductor package", (Shin, [0034]).
Regarding dependent claim 9, Gao, as previously modified by O’Brien, teaches the integrated circuit structure of claim 6. However, as previously combined, they do not teach wherein the thermal conductive via does not electrically couple electrical features.
However, in the same field of endeavor, Shin teaches wherein the thermal conductive via does not electrically couple electrical features (Fig. 10, Fig. 11, VST; [0075], "The wiring structure 602 may include a thermal conductive layer TL, a thermal conductive pad TP, and a thermal conductive via structure VST that connects the thermal conductive layer TL to the thermal conductive pad TP.", (Only thermal parts are connected, no mention of connection to electrical parts)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the integrated circuit structure as described by the combination of Gao and O’Brien with the lack of electrical coupling of Shin for "allowing regulation of the temperature of the first semiconductor apparatus", (Shin, [0041]).
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over O'Brien (US 20220199799 A1), in view of Gao (US 20150255364 A1).
Regarding independent claim 11, O’Brien teaches a computing device, comprising: a board (Fig. 7, 702; [0094], "The IC device assembly 700 includes a number of components disposed on a circuit board 702…"); and a component coupled to the board (Fig. 7, 702; [0094], "The IC device assembly 700 includes components disposed on a first face 740 of the circuit board 702 and an opposing second face 742 of the circuit board 702."), the component including an integrated circuit structure (Fig. 7; [0094], "Referring to FIG. 7, an IC device assembly 700 includes components having one or more integrated circuit structures described herein."), and comprising: a front side structure comprising: a device layer comprising a plurality of fin-based or nanowire- based transistors (Fig. 6, 640; [0084], "The transistors 640 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include Fin-based transistors...", Fig. 6, 640; [0084], "The transistors 640 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include Fin-based transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.").
However, O’Brien does not teach and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors; a backside structure below the plurality of fin-based or nanowire-based transistors; a carrier wafer or substrate bonded to the front side structure; and a thermal conductive via that extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.
However, in the same field of endeavor, Gao teaches a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors (Fig. 1A, M1,2,3,4,5; [0026], "In this example, there are five levels of metallization, namely M1, M2, M3, M4, and M5; however, in other configurations there may be fewer or more levels of metallization."); a backside structure below the plurality of fin-based or nanowire-based transistors; a carrier wafer or substrate bonded to the front side structure (Fig. 1A, 12; [0071], "For a signal via structure, there is a substrate 12-to-liner 15 interface 804…"); and a thermal conductive via that extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate (Fig. 1A, 18, 21; [0071], "However, for a highly thermally conductive via conductor 21, thermal resistance thereof may be small enough in comparison to these other thermal resistances to be excluded from a thermal resistance determination.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the computing device of O’Brien with the backside structure of Gao "for conducting heat in a generally vertical direction", (Gao, [0047]).
Regarding dependent claim 12, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches comprising the plurality of fin-based transistors (Fig. 6, 640; [0084], "The transistors 640 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include Fin-based transistors...").
Regarding dependent claim 13, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches comprising the plurality of nanowire-based transistors (Fig. 6, 640; [0084], "The transistors 640 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include Fin-based transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.").
Regarding dependent claim 14, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches further comprising a memory coupled to the board ([0098], "Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.").
Regarding dependent claim 15, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches further comprising a communication chip coupled to the board (Fig. 8, 806; [0102], "The board 802 may include a number of components, including but not limited to a processor 804 and at least one communication chip 806.").
Regarding dependent claim 16, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches wherein the component is a packaged integrated circuit die ([0126], "Example embodiment 15: The computing device of example embodiment 11, 12, 13 or 14, wherein the component is a packaged integrated circuit die.").
Regarding dependent claim 17, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches further comprising a battery coupled to the board (Fig. 8; [0103], "These other components include, but are not limited to…a battery…").
Regarding dependent claim 18, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches further comprising a display coupled to the board (Fig. 8; [0103], "These other components include, but are not limited to…a display…").
Regarding dependent claim 19, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches further comprising a camera coupled to the board (Fig. 8; [0103], "These other components include, but are not limited to…a camera…").
Regarding dependent claim 20, O’Brien, as previously modified by Gao, teaches the computing device of claim 11, and further teaches wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Fig. 8, 804, 806; [0102], "The board 802 may include a number of components, including but not limited to a processor 804 and at least one communication chip 806.", [0103], "These other components include, but are not limited to…a digital signal processor...").
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160372552 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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