Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
NONFINAL OFFICE ACTION
This Office Action addresses U.S. Patent Application No. 18/223,856, which is filed as a reissue of U.S. Patent Application No. 16/811,209 (hereinafter, the '209 application), entitled “SEMICONDUCTOR MEMORY DEVICE”, which issued as U.S. Patent No. 11,069,405 (hereinafter, the '405 patent). The '405 patent claims priority to JP 2019-166252.
Claims 1-18 are pending.
Claims 1-14 were issued in the '405 patent.
Claims 15-18 are newly presented with this reissue application.
PRIOR OR CONCURRENT PROCEEDINGS
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which the patent is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
In accordance with MPEP § 1406, the examiner has reviewed and considered the prior art made of record during the prosecution of the original patent. Such prior art need not be resubmitted in this reissue application unless applicant desires the information to be printed on a patent issuing from this reissue application.
CONSENT
This Consent of Assignee is properly signed in accordance with MPEP 325(V)(A).
DRAWING OBJECTIONS
The drawings filed July 19, 2023 are objected to because they are not in accordance with 37 CFR 1.84(p)(3), which states that numbers, letters, and reference characters:
(1) “must measure at least .32 cm (1/8 inch) in height.” However, much of the text in subscript does not meet this requirement.
(2) “should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines.” However, much of the text crosses or mingles with the lines. Note some examples below:
PNG
media_image1.png
126
209
media_image1.png
Greyscale
or
PNG
media_image2.png
340
176
media_image2.png
Greyscale
or
PNG
media_image3.png
113
182
media_image3.png
Greyscale
Corrected drawing sheets are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended.
Each amended drawing should be labeled “Amended”, for example:
FIG. 1
(Amended)
Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Note 37 CFR 1.173 for reissue drawing amendments. Note also MPEP 1413.
SPECIFICATION
The disclosure is objected to because of the following informalities:
(1) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
(2) The amendment filed July 19, 2023 adds “all of” to the first paragraph. Either “all of” or “the entire contents of” should be removed.
(3) The specification is replete with errors in English idiom and must be thoroughly revised. Some examples are:
(a) “Semiconductor memories including resistive change elements such as phase-change memory elements (hereinafter also referred to as “phase-change material (PCM) elements”) serving as storage elements disposed in intersections of wirings are known.”
(b) The use of “wiring” and “wirings” throughout. This should be “line” or “lines”, as appropriate.
(c) “in a stacking manner”
(d) “may possibly contact the contact”
(d) “A semiconductor memory capable of preventing an increase in chip size if having an increased number of layers will then be described by referring to embodiments below”
Appropriate correction is required.
CLAIM SUPPORT
Applicant must provide an explanation of the support in the disclosure of the patent for the changes made to the claims. The explanation of support must be on page(s) separate from the page(s) containing the amendment.
Pages 17-18 of the remarks attached to the amendment of July 19, 2023 include a list of citations in support of the new claims.
However, these citations are quite general (e.g., “New claim 15 includes subject matter supported at least by Fig. 2 of the '405 patent, having a corresponding description, e.g., at col. 7:45-67, col. 8:15-63, and col. 9:4-26, among other portions of the '405 patent”), and all of the citations are matched with claim numbers only. The citations do not show where each new limitation of each new claim may be found in the disclosure.
An explanation of support for each of limitations of the amended claims is required in response to this Office action.
Note MPEP 1411.02. Note also MPEP 1453(V)(D) for examples of proper support, wherein a separate citation is provided for each new limitation of each claim.
CLAIM OBJECTIONS
Claims 1-18 are objected to because “wiring” and “wirings” is not proper idiom. The electrical paths in semiconductors are called “lines”. Whereas wiring is used to connect external structures, within the memory, for example, “word lines” and “bit lines” are used. Thus, throughout claims 1-19, either “line” or “lines” should be used, as appropriate.
OBJECTIONS BASED ON DEFECTIVE OATH/DECLARATION
The statement of error in the declaration filed August 22, 2023 is as follows:
“At least one error is that the Applicant claimed less than the Applicant had a right to claim. Original claim 1 is directed to a semiconductor memory device comprising first through eighteenth wirings. Applicant is entitled to broader claims including claims directed to semiconductor memory devices comprising first through tenth wirings, as recited in new claim 15. Further, original claim 1 additionally recites first through third contacts. Applicant is entitled to broader claims including claims directed to semiconductor memory devices comprising ‘a first contact electrically connected to the portion of the tenth wiring and extending in the second direction to pass through a region between the sixth wiring and the seventh wiring and a region between the fourth wiring and the fifth wiring, the first contact being electrically connected to the portion of the first wiring,’ as recited in new claim 15.”
The reissue oath/declaration filed with this application is objected to as defective (see 37 CFR 1.175 and MPEP § 1414) because of the following:
(1) The statement of error states that “Original claim 1 is directed to a semiconductor memory device comprising first through eighteenth wirings” and that “Applicant is entitled to broader claims”. However, that error was already corrected by original patent claim 12, which comprises first through twelfth wirings.
(2) The statement of error states that “Further, original claim 1 additionally recites first through third contacts” and that “Applicant is entitled to broader claims”. However, that error was already corrected by original patent claim 12, which comprises “a first contact electrically connected to a portion of the eighth wiring, and passing through a region between the fourth wiring and the fifth wiring and a region between the second wiring and the third wiring.”
REJECTIONS BASED ON DEFECTIVE OATH/DECLARATION
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. §251 that form the basis for the rejections under this section made in this Office action:
(a) IN GENERAL.—Whenever any patent is, through error, deemed wholly or partly inoperative or invalid, by reason of a defective specification or drawing, or by reason of the patentee claiming more or less than he had a right to claim in the patent, the Director shall, on the surrender of such patent and the payment of the fee required by law, reissue the patent for the invention disclosed in the original patent, and in accordance with a new and amended application, for the unexpired part of the term of the original patent. No new matter shall be introduced into the application for reissue.
Defective Reissue Declaration
Claims 1-18 are rejected as being based upon a defective reissue declaration under 35 U.S.C. §251. The declaration is defective for all of the reasons set forth above with regard to the objections to the declaration. See 37 CFR 1.175.
Original Patent Requirement
Claims 15-18 are rejected as failing to satisfy the original patent requirement of 35 USC § 251.
The reissue claims must be for the same invention as that disclosed as being the invention in the original patent, as required by 35 U.S.C. 251. The entire disclosure, not just the claim(s), is considered in determining what the patentee objectively intended as the invention. The determination of the original patent requirement is “an essentially factual inquiry confined to the objective intent manifested by the original patent.” In re Amos, 953 F.2d 613, 618, 21 USPQ2d 1271, 1274 (Fed. Cir. 1991) (quoting In re Rowand, 526 F.2d 558, 560, 187 USPQ 487, 489 (CCPA 1975)) (emphasis added); See also In re Mead, 581 F.2d 251, 256, 198 USPQ 412, 417 (CCPA 1978).
Pages 17-18 of the remarks attached to the amendment of July 19, 2023 include a list of citations in support of claims 15-18. These citations point to Figure 2 and columns 7-9. Note that Figure 2 is a perpendicular view of Figure 1. Note also that Figures 1 and 2 and columns 7-9 describe the first embodiment of the '405 patent.
In the first embodiment, “The semiconductor memory 10 1 includes a plurality of (nine in FIG. 1) bit lines BL14 to BL112, a plurality of (nine in FIG. 1) PCM elements 1114 to 11112, and a plurality of (two in FIG. 1) word lines WL11 and WL12. The bit lines BL14 to BL112, the PCM elements 1114 to 11112, and the word lines WL11 and WL12 are disposed at different levels in a z direction (the vertical direction in FIG. 1).”
Further, “a bit line (for example, the bit line BL14) of the first semiconductor memory 10 1 on the bottom and a bit line (for example, the bit line BL44) of the fourth semiconductor memory 10 4, the location of which along the x direction is the same as the location of the bit line of the first semiconductor memory 10 1, are connected to each other through the contact VB44, and a bit line (for example, the bit line BL34) of the third semiconductor memory 10 3 and a bit line (for example, the bit line BL64) of the sixth semiconductor memory 10 6, the location of which along the x direction is the same as the location of the bit line of the third semiconductor memory 10 3, are connected to each other through the contact VB64. In other words, a bit line of the ith (i=1, 2, 3, 4) semiconductor memory and a bit line of the (i+3)th semiconductor memory, the location of which along the x direction is the same as the bit line of the ith semiconductor memory, are electrically connected to each other through a contact.”
The disclosure of the '405 patent does not support further limiting the number of wirings. The intent of the original patent was to prevent an increase in chip size. As noted in column 1, lines 61-64, “If the divided word lines are not connected by using another wiring, additional transistors may be needed to drive the divided word lines, which also increases the chip size.”
Consequently, new claims 15-18, which lack the required wiring to effectively reduce chip size, do not meet the original patent requirement of § 251.
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
An application may include one or more claim limitations that use the words “means for” and also limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) use(s) a generic placeholder.
Three Prong Analysis
To invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, a claimed phrase must meet the three prong analysis as set forth in MPEP § 2181, subsection I.
(A) Regarding Prong (A), the MPEP states:
the claim limitation uses the term "means" or "step" or a term used as a substitute for "means" that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function....
The claim limitations listed below do not use the language "means" or "step". However, each of these may be found to be a generic placeholder.
semiconductor memory device
wirings
resistive change elements
contact
driving circuit
Thus, these limitations meet Prong (A) of the analysis.
(B) Regarding Prong (B), the MPEP states:
the term "means" or "step" or the generic placeholder is modified by
functional language, typically, but not always linked by the transition word "for" (e.g., "means for") or another linking word or phrase, such as "configured to" or "so that"...
The claim limitations listed below may be modified by functional language, as shown.
semiconductor memory device (not modified by functional language)
wirings (not modified by functional language)
resistive change elements (not modified by functional language)
contact (not modified by functional language)
driving circuit (“configured to”)
Any limitations which have been marked “not modified by functional language” do not meet Prong (B) and will not be further considered in this analysis. All other limitations meet Prong (B) of the analysis and must be considered in the following step.
(C) Regarding Prong (C), the MPEP states:
the term "means" or "step" or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
With regard to where the limitations may be found in the disclosure:
driving circuit (see below with regard to circuitry)
Note: With regard to the claimed driving circuit(s), the circuitry as claimed, combined with a description of the function of the circuits (switching on power), provides sufficient structure to one of ordinary skill in the art. See Mass. Inst. of Tech., 462 F.3d at 1355-1356, 80 USPQ2d at 1332 (“circuitry” is generally determined to have sufficient structure).
Thus, the limitations listed above do not meet Prong (C) of the analysis and thus do not invoke 35 U.S.C. § 112, 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph.
PRIOR ART
The prior art of record that appears most relevant to the present claims was previously cited during the prosecution of the '405 patent. These include:
Inuzuka et al., JP2019169214A
Jeong et al., U.S. Patent Application No. 2019/0140022
Sonehara, U.S. Patent No. 9019748
None of these references appear to teach or suggest, either alone or in combination, each and all of the features of claims 1-14.
As an example with regard to the broadest claim 12, the prior art does not teach or suggest the claimed semiconductor memory device comprising:
a plurality of first wirings disposed at a first level and extending in a first direction;
a second wiring and a third wiring disposed at a second level, a position of which in a second direction intersecting with the first direction is different from that of the first level, the second wiring and the third wiring extending in a third direction that intersects with the first direction and the second direction, and being separated from each other;
a plurality of first resistive change elements each including a first terminal and a second terminal and disposed between one of the first wirings and one of the second wiring and the third wiring, the first terminal being electrically connected to the one of the first wirings, and the second terminal being electrically connected to the one of the second wiring and the third wiring;
a fourth wiring disposed to be in contact with a face of the second wiring opposite to the first wirings and extending in the third direction;
a fifth wiring disposed to be in contact with a face of the third wiring opposite to the first wirings, extending in the third direction, and separated from the fourth wiring;
a plurality of sixth wirings disposed at a third level and extending in the first direction, the second level being between the first level and the third level;
a plurality of second resistive change elements each including a third terminal and a fourth terminal and disposed between one of the fourth wiring and the fifth wiring and one of the sixth wirings, the third terminal being electrically connected to the one of the fourth wiring and the fifth wiring, and the fourth terminal being electrically connected to the one of the sixth wirings;
a plurality of seventh wirings disposed to correspond to the sixth wirings and extending in the first direction, each of the seventh wirings being disposed to be in contact with a face of corresponding one of the sixth wirings opposite to the second resistive change elements;
an eighth wiring and a ninth wiring disposed at a fourth level, extending in the third direction, and separated from each other, the third level being between the fourth level and the second level;
a plurality of third resistive change elements each including a fifth terminal and a six terminal and disposed between one of the seventh wirings and one of the eighth wiring and the ninth wiring, the fifth terminal being electrically connected to the one of the seventh wirings, and the six terminal being electrically connected to the one of the eighth wiring and the ninth wiring;
a tenth wiring disposed to be in contact with a face of the eighth wiring opposite to the seventh wirings and extending in the third direction;
an eleventh wiring disposed to be in contact with a face of the ninth wiring opposite to the seventh wirings and extending in the third direction, and separated from the tenth wiring;
a plurality of twelfth wirings disposed at a fifth level and extending in the first direction, the fourth level being between the fifth level and the third level;
a plurality of fourth resistive change elements each including a seventh terminal and an eighth terminal and disposed between one of the tenth wiring and the eleventh wiring and one of the twelfth wirings, the seventh terminal being electrically connected to the one of the tenth wiring and the eleventh wiring, and the eighth terminal being electrically connected to the one of the twelfth wirings; and
a first contact electrically connected to a portion of the eighth wiring, and passing through a region between the fourth wiring and the fifth wiring and a region between the second wiring and the third wiring.
CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to B. James Peikari at telephone number 571-272-4185. The examiner can normally be reached on Mon-Fri from 8:30am to 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Kosowski, SPE Art Unit 3992, can be reached at 571-272-3744.
Information regarding the status of published reissue applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users.
To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov.
Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to the Central Reexamination Unit at telephone number (571) 272-7705.
/B. James Peikari/
Primary Examiner, Art Unit 3992
Conferees:
/DENNIS G BONSHOCK/Primary Examiner, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992