DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/02/2026 has been entered.
Applicant’s amendment dated 09/02/2026 has been received and entered. By the amendment, claims 1-15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 7 and 9-15 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kikuchi et al., US 2020/0388637 A1.
Claim 1 is anticipated by Kikuchi et al. figures 1, 2A-2B and accompanying text which discloses a display device comprising:
. a transistor 20 comprising a semiconductor layer 7, a gate insulating layer 9, a gate electrode GE, a first conductive layer M1 and a second conductive layer PE
. a liquid crystal element comprising the second conductive layer PE, a third conductive layer CE and a liquid crystal (inherently forming in a liquid crystal display LCD panel)
. a first insulating layer 5 comprising a first side surface (lower side surface), wherein the first side surface is positioned over the first conductive layer M1, wherein the semiconductor layer 5 is in contact with a top surface (top side surface) of the first conductive layer M1 and the first side surface, wherein the gate insulating layer comprises a portion facing the first side surface with the semiconductor layer positioned between the gate insulating layer and the first side surface (fig. 2B)
. wherein the gate electrode GE comprises a portion facing the first side surface with the semiconductor layer 7 and the gate insulating layer 9 positioned between the gate electrode GE and the first side surface (fig. 2B)
. wherein the second conductive layer PE is positioned over the first insulating layer 5 and the second conductive layer PE is in contact with the semiconductor layer 7 (PE electrical contacting to 7 thru DE)(fig. 2B)
. wherein the third conductive layer CE is positioned over the first insulating layer 5 and comprises a portion overlapping and non-overlapping with the second conductive layer PE in a plan view (fig. 2B)
. wherein the semiconductor layer 7 comprises an oxide semiconductor film ([0010])
. wherein the second conductive layer CE comprises an oxide conductive film ([0223]).
Re claim 2, Kikuchi et al. further disclose the first insulating layer comprising an opening (where the semiconductor 7 contacts to the first conductive layer M1) and a first side surface positioned in the opening (fig. 2B).
Re claim 3, wherein the third conductive layer PE is positioned over the second conductive layer CE and comprises an oxide conductive film ([0223]), and wherein the gate insulating layer 9 comprises a portion positioned between the third conductive layer PE and the second conductive layer CE.
Re claim 4, wherein the third conductive layer PE is provided in contact with a top surface of the gate insulating layer (fig. 2B).
Re claim 5, Kikuchi et al. further disclose a second insulating layer 17 over the gate electrode GE, wherein the third conductive layer PE comprises a portion overlapping with the second conductive layer CE with the gate insulating layer, and the second insulating layer 17 positioned between the third conductive layer PE and the second conductive layer CE (fig. 2B).
Re claim 7, Kikuchi et al. further disclose a second insulating layer 17 over the third conductive layer CE, wherein the second conductive layer PE comprises a portion overlapping with the third conductive layer CE with the second insulating layer 17 positioned between the second conductive layer PE and the third conductive layer CE (fig 2B).
Re claim 9, wherein a second insulating layer 17 over the third conductive layer CE, wherein the second conductive layer PE comprises a portion overlapping with the third conductive layer CE with the second insulating layer 17 positioned between the second conductive layer and the third conductive layer (fig 2B).
Re claims 10 and 11, wherein the gate electrode GE comprises a portion overlapping with the first conductive layer M1 with the semiconductor layer 7 and the gate insulating layer 9 positioned between the gate electrode GE and the first conductive layer M1.
Re claims 12 and 13, wherein the gate electrode GE comprises a portion overlapping with the second conductive layer PE with the semiconductor layer 7 and the gate insulating layer 9 positioned between the gate electrode GE and the first conductive layer M1.
Re claims 14 and 15, wherein a second insulating layer 17 over the gate electrode GE, wherein the second insulating layer 17 is configured to function as a spacer (e.g., spacer between PE and CE).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi et al., US 2020/0388637 A1.
Re claim 6, Kikuchi et al. disclose the claimed invention as described above except for the third conductive layer comprising a portion overlapping with the gate electrode. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ a third conductive layer having a portion overlapping a gate electrode, since it has been held that rearranging parts of an invention involves only routine skill in the display art. In re Japikse, 86 USPQ 70.
Re claim 8, Kikuchi et al. disclose the claimed invention as described above except for the gate insulating layer comprises a portion positioned between the third conductive layer and the second conductive layer. It would have been an obvious matter of design choice to employ a gate insulating layer having a portion positioned between pixel and common conductive layer, since the such insulating layer appears to perform equally well with any interlayer insulating layer between pixel and common electrodes for insulated purposes.
Response to Arguments
Applicant's arguments filed 02/11/2026 have been fully considered but they are not persuasive.
. Applicant’s arguments are as following:
a. First, Kikuchi fails to teach the second conductive layer PE being a common element that is shared by both the TFT 20 and the liquid crystal display element.
b. Second, Kikuchi fails to teach the feature of the conductive layer PE is formed in a layer above upper insulating layer and in contact the semiconductor layer.
c. Third and Fourth, Kikuchi’s fig. 2B fails to teach or suggest that the gate electrode, gate insulating layer comprises a portion facing the first side surface of layer; instead, the gate electrode and the gate insulating layer appears to only include a portion facing a top surface.
d. Finally, Kikuchi has not been shown to teach the second conductive layer comprises a portion overlapping and a portion not overlapping with the third conductive layer in a plan view.
. Examiner respectfully disagrees with Applicant’s viewpoint. Particularly,
a. Kikuchi et al. second conductive layer PE is a pixel electrode which is inherently a part of the LCD element, in addition, the pixel electrode PE is connecting to the transistor 20 thru the drain electrode DE that a part of the transistor; in other words, the pixel electrode would be a part of the transistor as a common element sharing by both the transistor and the LCD element as claimed.
b. as stated above, although the second conductive layer PE does not directly connected to the semiconductor layer, the second conductive layer PE do connect to the semiconductor thru the drain electrode DE as shown in fig 2B.
c. in response to Applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., bottom surface) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
d. although Kikuchi et al. do not show any plan view to show the limitation of the second conductive layer comprising a portion overlapping and non-overlapping with the third conductive layer, the such limitation can be read over the side view as well, e.g., part of PE overlapping CE (PE on left side of the contact hole CHp) and part of PE not overlapping the CE (PE on right side of the contact hole CHp)(fig. 2B).
Accordingly, the rejection of claims 1-5, 7, 9-15 and 6, 8 stand as stated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US 2018/0122832) disclose a pixel electrode overlapping/not overlapping the common electrode (see figs 2-3).
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/DUNG T NGUYEN/Primary Examiner, Art Unit 2871
