DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II claims 13-18 in the reply filed on 05/21/2026 is acknowledged.
Claim Status
Claims 13-32 are pending, claims 1-12 are withdrawn, and claims 19-32 are newly added.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13-20, 22, 26-27 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yasuda US 20110292945 A1, hereinafter Yasuda in view of Burstein US 20180267919 A1 (publication date 2018-09-20), hereinafter Burstein.
Regarding claim 13, Yasuda teaches a network adapter, comprising: a network interface operatively coupled to a communication network; packet processing circuitry operatively coupled to the network interface, wherein the packet processing circuitry is configured to:
(Yasuda: Summary, Fig. 15 and para. [0133] server is provided with the program processing device 100 and the network interface device 200. The program processing device 100 is provided with a CPU 110 and a storage device 120. The CPU 110 executes various software programs including the application and the OS. The network protocol stack 10 is a part of the kernel program of the OS and realized by software. The network interface device 200 is the network interface card (NIC) connected to the program processing device 100)
receive, via the network interface, a subset of a plurality of data packets, wherein the subset comprises in-order data packets (In-Order packet PKT-I);
(Yasuda: para. [0043 & 0046] In-Order packet PKT-I is a packet received in expected order. Para. [0047] receiving packet PKT is the In-Order packet PKT-I of a certain flow and the Out-of-Order packet PKT-O of the same flow is already stored in the buffer section 4, the reordering section 3 performs the following processing. Para. [0051] In-Order packet PKT-I arrives, all the packets PKT of the flow are transmitted to the network protocol stack 10 irrespective of an arranging state of the packets PKT of the flow)
aggregate the subset (In-Order packet PKT-I) of the plurality of data packets to be stored in a first buffer;
(Yasuda: para. [0047] receiving packet PKT is the In-Order packet PKT-I of a certain flow and the Out-of-Order packet PKT-O of the same flow is already stored in the buffer section 4)
receive, subsequently, an out-of-order data packet (Out-of-Order packet PKT-O);
(Yasuda: para. [0043 & 0046] in the case where the receiving packet PKT is the Out-of-Order packet PKT-O, the reordering section 3 stores the receiving packet PKT-O in the buffer section 4 as far as possible. At this time, the receiving packet PKT-O is associated with a flow to which the packet belongs, and stored in the buffer section 4. That is, the Out-of-Order packet PKT-O is temporarily stored (buffered) in the buffer section 4 while being associated with the flow).
It is noted that Yasuda does not explicitly disclose: cause the first strided buffer to be processed in response to receiving the out-of- order data packet; and generate a first completion notification indicating that the subset of the plurality of data packets in the first strided buffer has been processed.
However, Burstein from the same or similar fields of endeavor teaches the use of: strided buffer (Burstein: Fig. 2 and para. [0043] Each WQE 64 comprises one or more scatter entries (referred to as SE0, SE1, etc., in FIG. 2). Each scatter entry points to the base address of a corresponding buffer 66 that has been reserved in memory 34. Each buffer 66 is divided into an integer number of strides 68, of a predefined size. The stride size may be chosen, for example, on the basis of the expected data size of incoming packets on QPs 60, so that small packets consume a single stride, while larger packets consume multiple strides. All buffers 66 may conveniently be of the same size, and thus contain the same number of strides, or they may be of different sizes)
cause the first strided buffer to be processed (completion) in response to receiving the out-of- order data packet (packets are received out of order);
(Burstein: para. [0062] When multiple strides are allocated in advance to accommodate the packets in a multi-packet message, processing circuitry 44 can make use of the allocation in delivering the message data to CPU 32 in the proper order, even when the packets are received out of order or are received intermittently on different QPs that share the same SRQ. para. [0048] After it has finished writing the data from each packet 70 to the appropriate buffer 66, processing circuitry 44 writes a completion report, such as a completion queue entry (CQE) 74, to a completion queue 72 in memory 34. CQE 74 indicates the QP 60 to which the packet was addressed and, in the case of multi-packet messages, whether the packet was the first, middle, or last packet in the message. para. [0068] When packet processing circuitry 44 has finished writing the data in the current packet to memory 34, it writes a CQE 74 to completion queue 72, at a completion step 92. (CQE may be issued for each message or scatter entry in a WQE, for example, as explained above.) Driver program 50 reads CQEs 74, at a CQE reading step 94, and thus tracks the use of buffers 66 and consumption of the corresponding WQEs 64. Driver program 50 may also inform clients 46 when send operations directed to their respective QPs 60 are completed (including multi-packet send operations))
and
generate a first completion notification (completion report) indicating that the subset of the plurality of data packets in the first strided buffer has been processed.
(Burstein: para. [0048] After it has finished writing the data from each packet 70 to the appropriate buffer 66, processing circuitry 44 writes a completion report, such as a completion queue entry (CQE) 74, to a completion queue 72 in memory 34. CQE 74 indicates the QP 60 to which the packet was addressed and, in the case of multi-packet messages, whether the packet was the first, middle, or last packet in the message. para. [0068] When packet processing circuitry 44 has finished writing the data in the current packet to memory 34, it writes a CQE 74 to completion queue 72, at a completion step 92. (CQE may be issued for each message or scatter entry in a WQE, for example, as explained above.) Driver program 50 reads CQEs 74, at a CQE reading step 94, and thus tracks the use of buffers 66 and consumption of the corresponding WQEs 64. Driver program 50 may also inform clients 46 when send operations directed to their respective QPs 60 are completed (including multi-packet send operations)) Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Burstein in the apparatus of Yasuda. One of ordinary skill in the art would be motivated to do so for receive queue model can be useful in many data communication scenarios, but it is particularly advantageous in handling incoming data traffic that can include both small and large packets and may be characterized by unpredictable bursts. The stride-based buffers and work items enable the host processor and NIC to handle such traffic efficiently, in terms of both memory footprint and overhead incurred by the host processor and bus (Yasuda: para. [0036]).
Regarding claim 14, Yasuda and Burstein teach the network adapter of Claim 13, wherein the out-of-order data packet is associated with the plurality of data packets. (Yasuda: para. [0043 & 0046] in the case where the receiving packet PKT is the Out-of-Order packet PKT-O, the reordering section 3 stores the receiving packet PKT-O in the buffer section 4 as far as possible. At this time, the receiving packet PKT-O is associated with a flow (corresponds to claim limitation “associated with the plurality of data packets”) to which the packet belongs, and stored in the buffer section 4)
Regarding claim 15, Yasuda and Burstein teach the network adapter of Claim 13, Yasuda does not explicitly teach: wherein the packet processing circuitry is configured to: determine whether the plurality of data packets is received within a predetermined time period; determine that only a first subset of the plurality of data packets is received within the predetermined time period; aggregate the first subset of the plurality of data packets to be stored in a second strided buffer; process the second strided buffer; and generate a second completion notification indicating that the first subset of the plurality of data packets in the second strided buffer has been processed.
However, Burstein from the same or similar fields of endeavor teaches the use of: wherein the packet processing circuitry is configured to: determine whether the plurality of data packets is received within a predetermined time period (timer period); determine that only a first subset of the plurality of data packets (messages) is received within the predetermined time period; aggregate the first subset of the plurality of data packets to be stored in a second strided buffer (number of available buffers or WQEs in the queue); process the second strided buffer; (Burstein: para. [0061] Each new message or LRO session (which is regarded as a type of “message” in the present context) initiated by packet processing circuitry 44 reserves an allocation of fixed size, containing a certain number of strides, in a corresponding buffer, and each such reservation holds a timer for buffer release. The timer starts when the buffer is reserved and closes when the reserved allocation is full. When the contiguous allocation has been consumed or when timer expires (when the contiguous allocation has not been fully consumed by the expiration of the predefined timeout), circuitry 44 issues a CQE 74 so that CPU 32 will process the data that have been written to the buffer. Unused strides remaining in a given buffer can be used by another message or a subsequent session. Multiple messages or sessions can run in parallel, each with its own buffer, with the number of messages or sessions limited by the number of available buffers or WQEs in the queue) and generate a second completion notification indicating that the first subset of the plurality of data packets in the second strided buffer has been processed. (Burstein: para. [0048-0056] CQE 74 indicates the QP 60 to which the packet was addressed and, in the case of multi-packet messages, whether the packet was the first, middle, or last packet in the message. para. [0014] a respective last packet, the method includes writing respective completion reports from the NIC to the memory only after writing the data from the respective last packet in each of the first and second messages to the memory. Typically, the completion reports contains pointers to the strides to which the data in each of the messages were written). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Burstein in the apparatus of Yasuda. One of ordinary skill in the art would be motivated to do so for receive queue model can be useful in many data communication scenarios, but it is particularly advantageous in handling incoming data traffic that can include both small and large packets and may be characterized by unpredictable bursts. The stride-based buffers and work items enable the host processor and NIC to handle such traffic efficiently, in terms of both memory footprint and overhead incurred by the host processor and bus (Yasuda: para. [0036]).
Regarding claim 26, Yasuda and Burstein teach the network adapter of Claim 13, wherein the packet processing circuitry is further configured to determine that the subset comprises the in-order data packets based on: a determination that the subset of the plurality of data packets is associated with a first incoming message; (Yasuda: para. [0047] in the case where the receiving packet PKT is the In-Order packet PKT-I of a certain flow and the Out-of-Order packet PKT-O of the same flow is already stored in the buffer section 4) and a determination that the subset of the plurality of data packets is in a same sequence as they were sent.
(Yasuda: para. [0078] and Fig. 7 step s40 reordering block 30 determines whether or not the receiving packet PKT is the In-Order packet PKT-I based on the expected sequence number ESQN of the first flow and the sequence number of the receiving packet PKT. Specifically, the reordering block 30 compares the expected sequence number ESQN and the sequence number of the receiving packet PKT. In the case where the following conditional expression (2) is satisfied, that is, in the case where the sequence number of the receiving packet PKT matches with the expected sequence number ESQN, the reordering block 30 determines that the receiving packet PKT is the In-Order packet PKT-I)
Regarding claim 27, Yasuda and Burstein teach the network adapter of Claim 13, wherein the subset of the plurality of data packets is associated with a first incoming message, and wherein the out-of-order data packet is associated with a second plurality of data packets (different flows) of a second incoming message that is distinct from the first incoming message. (Yasuda: para. [0068] The packet storage region 65 may be provided for one flow, or may be provided for a plurality of flows. In the case where the plurality of packet storage regions 65 is provided, the Out-of-Order packets PKT-O of the plurality of different flows can be buffered in parallel)
Regarding claim 29, Yasuda and Burstein teach the network adapter of Claim 13, Yasuda does not explicitly teach: wherein causing the first strided buffer to be processed comprises writing the subset of the plurality of data packets from the first strided buffer to memory indices associated with a host memory.
However, Burstein from the same or similar fields of endeavor teaches the use of: wherein causing the first strided buffer to be processed comprises writing the subset of the plurality of data packets from the first strided buffer to memory indices (stride indexes) associated with a host memory. (Burstein: para. [0050-0056] In this latter case, CQE 74 typically contains further information to enable processes running on CPU 32 to parse and process the data that have been written to memory 34. For instance, the CQE may contain details of packets and/or messages scattered to be the buffer or buffers pointed to by the WQE in question, such as association between packets or messages and corresponding transport service instances (QPs or LRO sessions), stride indexes, and an indication whether each packet was the first, last or intermediate packet in a multi-packet message) Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Burstein in the apparatus of Yasuda. One of ordinary skill in the art would be motivated to do so for receive queue model can be useful in many data communication scenarios, but it is particularly advantageous in handling incoming data traffic that can include both small and large packets and may be characterized by unpredictable bursts. The stride-based buffers and work items enable the host processor and NIC to handle such traffic efficiently, in terms of both memory footprint and overhead incurred by the host processor and bus (Yasuda: para. [0036]).
Regarding claims 16-20 and 22, Yasuda and Burstein teach a method for processing data packets, the method comprising: (Yasuda: Summary, Fig. 15 and para. [0133] server is provided with the program processing device 100 and the network interface device 200. The program processing device 100 is provided with a CPU 110 and a storage device 120. The CPU 110 executes various software programs including the application and the OS. The network protocol stack 10 is a part of the kernel program of the OS and realized by software. The network interface device 200 is the network interface card (NIC) connected to the program processing device 100) and Yasuda and Burstein teach all the limitations as discussed in the rejection of claims 13-15, 26-27 and 29 and therefore method claims 16-20 and 22 are rejected using the same rationales.
Allowable Subject Matter
Claims 21, 23-25, 28 and 30-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please also PTO-892.
Shahar et al. US 20210081236 A1 in para. [0040] teaches tasks that complete in a different order than the order that they began execution are often reported to the completion queue with CQEs in the order they completed, which is not necessarily the order in which the associated WRs were posted to the WQ. Such out of order signaling of CQEs may lead to certain burdens on the producer of the WR. First, the CQEs must be reported for each WR. Since a CQE only indicates completion of its associated WR, and does not imply completion of other WRs, one CQE per WR is required. In a case where CQEs are reported in the order the WRs were posted, a CQE indicating a WR completion implicitly indicates completion of predecessor WRs.
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/WUTCHUNG CHU/Primary Examiner, Art Unit 2418
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