DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/20/2023 is being considered by the examiner.
Status of Claims
This office action is in response to "Claims filed on 12/29/2025". Applicant's amendments of claims 1, 2, 4, 11, 19 with the same reply have been entered by the Examiner. Upon entry of the amendments, claims 1-20 are pending wherein claims 1, 11 and 19 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently disclose a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between).
Claim(s) 1-3, 6-8, 11-15, 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura, Takeshi (US 2013/0082393 A1 hereinafter Nakamura).
Regarding Claim 1, Kawamura discloses in Fig 20-22: A semiconductor device, comprising:
a semiconductor layer (NS1) on a substrate (1S);
a first insulating layer (SO) on the semiconductor layer;
a first conductive structure (PL1), which is provided to penetrate the first insulating layer (SO) in a vertical direction perpendicular to a bottom surface of the substrate and is connected to the semiconductor layer (See Fig 20);
a second insulating layer (IL2) covering the first insulating layer and the first conductive structure;
a second conductive structure (CUF), which is provided to penetrate the second insulating layer (IL2) in the vertical direction and is connected to the first conductive structure; and
a diffusion barrier layer (IL1) covering the topmost surface of the first insulating layer (SO) in the vertical direction and extending to a side surface of the first conductive structure (PL1),
wherein the lowermost surface of the second conductive structure (CUF) is located at a height higher than the topmost surface of the first insulating layer (SO),
wherein the diffusion barrier layer (IL1) extends between the second insulating layer (IL2) and the first insulating layer (SO), and between the second insulating layer (IL2) and the first conductive structure (PL1), and
wherein the second insulating layer (IL2) and the first conductive structure (PL1) overlap each other in a horizontal direction parallel to the bottom surface of the substrate (1S) [0186-0193].
Regarding Claim 2, Kawamura discloses in Fig 20-22: The semiconductor device of claim 1, wherein the lowermost surface of the second conductive structure (CUF) is spaced apart from the topmost surface of the first insulating layer (SO).
Regarding Claim 3, Kawamura discloses in Fig 20-22: The semiconductor device of claim 1, wherein the first conductive structure (Titanium) [0120] and the second conductive structure comprise different materials from each other (Copper) [0128].
Regarding Claim 6, Kawamura discloses in Fig 20-22: The semiconductor device of claim 1, wherein: a top surface of the first conductive structure (PL1) is located at a first level, the first conductive structure has a first width, at the first level, the second conductive structure (CUF) has a second width, at the first level, and the second width is equal to or different from the first width (See Fig 22).
Regarding Claim 7, Kawamura discloses in Fig 20-22: The semiconductor device of claim 1, wherein the lowermost surface of the second conductive structure (CUF) is located at a height that is lower than or equal to a top surface of the first conductive structure (PL1) (See Fig 22).
Regarding Claim 8, Kawamura discloses in Fig 20-22: The semiconductor device of claim 1, wherein a top surface of the first conductive structure (PL1) is located at a first level, and wherein the first insulating layer (SO) is in contact with the diffusion barrier layer (IL1), at a height lower than the first level (See Fig 22).
Regarding Claim 11, Kawamura discloses in Fig 20-22: A semiconductor device, comprising:
a semiconductor layer (NS1) on a substrate (1S);
a first insulating layer (SO) on the semiconductor layer;
a first conductive structure (PL1), which is provided to penetrate the first insulating layer (SO) in a vertical direction perpendicular to a bottom surface of the substrate and is connected to the semiconductor layer;
a second insulating layer (IL2) covering the first insulating layer and the first conductive structure; and
a second conductive structure (CUF), which is provided to penetrate the second insulating layer (IL2) in the vertical direction and is connected to the first conductive structure (PL1), wherein the first insulating layer (Silicon oxide) and the second insulating layer (SiOC) include different materials from each other, and
wherein the lowermost surface of the second conductive structure (CUF) is spaced apart from a top surface of the first insulating layer (SO),
wherein the second insulating layer (IL2) is a single continuous layer, and
wherein the second insulating layer (IL2) and the first conductive structure (PL1) overlap each other in a horizontal direction parallel to the bottom surface of the substrate (1S) [0186-0193].
Regarding Claim 12, Kawamura discloses in Fig 20-22: The semiconductor device of claim 11, wherein the lowermost surface of the second conductive structure (CUF) is located at a height higher than the top surface of the first insulating layer (PL1).
Regarding Claim 13, Kawamura discloses in Fig 20-22: The semiconductor device of claim 11, wherein the first conductive structure (Titanium) [0120] and the second conductive structure include different materials from each other (Copper) [0128].
Regarding Claim 14, Kawamura discloses in Fig 20-22: The semiconductor device of claim 11, wherein the first conductive structure (PL1) contacts the second conductive structure (CUF) at a height higher than the top surface of the first insulating layer (SO) See Fig 22.
Regarding Claim 15, Kawamura discloses in Fig 20-22: The semiconductor device of claim 11, wherein the second insulating layer (IL2) is provided to fully enclose a side surface of the second conductive structure (CUF).
Regarding Claim 17, Kawamura discloses in Fig 20-22: The semiconductor device of claim 11, wherein the second insulating layer (IL2: SiOC) includes a low-k dielectric material.
Regarding Claim 18, Kawamura discloses in Fig 20-22: The semiconductor device of claim 11, further comprising: a diffusion barrier layer (IL1) covering the top surface of the first insulating layer (SO) and extending to a side surface of the first conductive structure (PL1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2021/0082809 A1 hereinafter Kim) in view of Nakamura, Takeshi (US 2013/0082393 A1 hereinafter Nakamura).
Regarding claim 19, Kim teaches in FIGS. 17, 25: a semiconductor device, comprising:
a substrate (100, [0013]) including a cell region (II, [0016]) and a peripheral region (III, [0016]);
a semiconductor layer (all elements between substrate 100 and capacitor electrode 530 in the cell region, and between substrate 100 and insulating layer 700 in the peripheral region, FIG. 25, as defined by Applicant) on the substrate (100);
wherein the semiconductor layer structure comprises:
an active pattern (105, [0020]) on the cell region (II);
a word line (gate structure 160, FIG. 17, [0024]) crossing the active pattern (105, see FIG. 17);
a bit line (305, FIG. 17, [0046]) extending in a direction (2ⁿᵈ direction, FIG. 17) crossing the word line (160, FIG. 17);
a capacitor (540, [0081]) connected to the active pattern (105), the capacitor (540) comprising a bottom electrode (510, [0083]), a top electrode (530, [0084]) on the bottom electrode (510), and a dielectric layer (520, [0084]) between the bottom and top electrodes (510 and 530, respectively);
a peripheral active pattern (108, [0020]) on the peripheral region (III); and
a peripheral word line (second gate structure 628, [0038]) on the peripheral active pattern (108).
Kim does not disclose: a first insulating layer on the semiconductor layer structure;
a first conductive structure, which is provided to penetrate the first insulating layer in a vertical direction perpendicular to a bottom surface of the substrate and is connected to the semiconductor layer;
a second insulating layer covering the first insulating layer and the first conductive structure; and
a second conductive structure, which is provided to penetrate the second insulating layer in the vertical direction and is connected to the first conductive structure,
wherein the lowermost surface of the second conductive structure is spaced apart from a top surface of the first insulating layer.
wherein the first insulating layer and the second insulating layer include different materials from each other, and
wherein the second insulating layer is a single continuous layer, and wherein the second insulating layer and the first conductive structure overlap each other in a horizontal direction parallel to the bottom surface of the substrate.
However, Nakamura in a similar device teaches in Fig 20-22: a first insulating layer (SO) on the semiconductor layer structure (NS1);
a first conductive structure (PL1), which is provided to penetrate the first insulating layer in a vertical direction perpendicular to the bottom surface of the substrate (1S) and is connected to the semiconductor layer;
a second insulating layer (IL2) covering the first insulating layer and the first conductive structure; and
a second conductive structure (CUF), which is provided to penetrate the second insulating layer in the vertical direction and is connected to the first conductive structure (PL1),
wherein the lowermost surface of the second conductive structure (CUF) is spaced apart from the top surface of the first insulating layer (SO).
wherein the first insulating layer (SO: silicon oxide) and the second insulating layer (IL2: SiOC) include different materials from each other, and
wherein the second insulating layer is a single continuous layer (See Fig 21), and wherein the second insulating layer (IL2) and the first conductive structure PL1) overlap each other in a horizontal direction parallel to the bottom surface of the substrate (1S).
References Kim and Nakamura are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kim with the specified features of Nakamura because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kim and Nakamura so that a first insulating layer on the semiconductor layer structure; a first conductive structure, which is provided to penetrate the first insulating layer in a vertical direction perpendicular to a bottom surface of the substrate and is connected to the semiconductor layer; a second insulating layer covering the first insulating layer and the first conductive structure; and a second conductive structure, which is provided to penetrate the second insulating layer in the vertical direction and is connected to the first conductive structure, wherein the lowermost surface of the second conductive structure is spaced apart from a top surface of the first insulating layer, wherein the first insulating layer and the second insulating layer include different materials from each other, and wherein the second insulating layer is a single continuous layer, and wherein the second insulating layer and the first conductive structure overlap each other in a horizontal direction parallel to the bottom surface of the substrate as taught by Nakamura in Kim’s device since, this improves electric performance of a semiconductor device, and, more particularly, is to reduce delay of a signal transmitted via a wiring [0012].
Regarding claim 20, Kim and Nakamura disclose the semiconductor device of claim 19. Kim teaches further comprising: an interlayer insulating layer (770, [0090]) covering the second insulating layer (740); and
a contact structure (783/784, [0090]), which is provided to penetrate the interlayer insulating layer (770) in the vertical direction and is connected to the second
conductive structure (753/754).
Claim(s) 9 (16) re rejected under 35 U.S.C. 103 as being unpatentable over Kawamura et al (US 2013/0082393 A1 hereinafter Kawamura) in view of Bark et al (US 2018/0261546 A1 hereinafter Bark).
Regarding Claim 9 (16), Kawamura discloses in Fig 20-22: The semiconductor device of claim 1 (11).
Kawamura does not disclose wherein the first insulating layer includes a hydrogen ion.
However, Bark in a similar device teaches wherein the first insulating layer (124) includes a hydrogen ion (124 may be formed of silicon-oxide based material such as TEOS, [0033]- [0034]).
References Kawamura and Bark are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawamura with the specified features of Bark because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawamura and Bark so that wherein the first insulating layer includes a hydrogen ion as taught by Bark in Kawamura’s device since, this provides a metal wiring structure capable of improving reliability by suppressing a resistance increase and a current leakage of metal wiring layers, and by suppressing electromigration of a metal [0004].
Allowable Subject Matter
Claims 4-5, 10 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 4, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the diffusion barrier layer includes a first top surface, which extends along the topmost surface of the first insulating layer, and a second top surface, which is placed at a height higher than the first top surface, and wherein the lowermost surface of the second conductive structure is located at a height higher than the first top surface of the diffusion barrier layer.” as recited in claim 4 in combination with the remaining features.
Dependent claim 5 contains allowable subject matter based on virtue of their dependencies
The most relevant prior art references, (US 2013/0082939 A1 to Nakamura Figs 20-22, substantially teaches the limitations of claim 4, with the exception of the limitations described in the preceding paragraph.
With respect to claim 10, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein: the second conductive structure is a first structure, the semiconductor device further comprises a second structure penetrating at least a portion of the second insulating layer, a top surface of the second structure is located at a height equal to a top surface of the first structure, and a bottom surface of the second structure is located at a height lower than a bottom surface of the first structure and higher than the top surface of the first insulating layer.” as recited in claim 10 in combination with the remaining features.
The most relevant prior art references, (US 2013/0082939 A1 to Nakamura Figs 20-22, substantially teaches the limitations of claim 10, with the exception of the limitations described in the preceding paragraph.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NISHATH YASMEEN whose telephone number is (571)270-7564. The examiner can normally be reached Mon-Fri 9AM-6PM.
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811
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