Prosecution Insights
Last updated: May 29, 2026
Application No. 18/224,830

HALF-BRIDGE GaN DRIVER WITH INTEGRATED GaN FET

Non-Final OA §102
Filed
Jul 21, 2023
Examiner
HERNANDEZ, WILLIAM
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
889 granted / 947 resolved
+25.9% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 7m
Avg Prosecution
13 currently pending
Career history
955
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
16.0%
-24.0% vs TC avg
§102
29.7%
-10.3% vs TC avg
§112
41.9%
+1.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 947 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bennett et al (USP 6,348,920). Regarding claim 1, Bennett’s Fig. 5 shows an integrated circuit comprising: a transistor (254); and a driver (252) coupled to a gate of the transistor, wherein the driver controls an operation of the transistor, wherein the driver is operable in a first configuration as a low- side gate driver (see abstract, lines 1-8) for a voltage regulator (when the load is a battery, a voltage regulator is inherent), wherein the transistor is operable in the first configuration as a low-side switch for the voltage regulator, wherein the driver is operable in a second configuration as a high-side gate driver for the voltage regulator, and wherein the transistor is operable in the second configuration as a high-side switch (see abstract, lines 1-8) for the voltage regulator. As to claim 2, Bennett’s Fig. 5 shows the integrated circuit of claim 1, wherein the transistor comprises Ga and N (Power FET 254 can be replaced by any power transistor including a GaN power transistor without affecting the overall functionality of the circuit). Allowable Subject Matter Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM HERNANDEZ whose telephone number is (571)272-8979. The examiner can normally be reached Mon to Fri; 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah M Youssef can be reached at (571) 270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM HERNANDEZ/Primary Examiner, Art Unit 2849
Read full office action

Prosecution Timeline

Jul 21, 2023
Application Filed
Feb 19, 2026
Non-Final Rejection mailed — §102
May 19, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12638483
METHOD OF MONITORING A CLOCK SIGNAL, CORRESPONDING DEVICE AND SYSTEM
2y 3m to grant Granted May 26, 2026
Patent 12640719
INTEGRATED CIRCUIT GLITCH DETECTION
1y 8m to grant Granted May 26, 2026
Patent 12633905
LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
2y 11m to grant Granted May 19, 2026
Patent 12633928
CLOCK SIGNAL FREQUENCY DIVIDER, PROCESSING SYSTEM, PROCESSING DEVICE, AND CLOCK SIGNAL FREQUENCY DIVIDING METHOD
2y 3m to grant Granted May 19, 2026
Patent 12633917
ISOLATED GATE DRIVER
2y 4m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.1%)
1y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 947 resolved cases by this examiner. Grant probability derived from career allowance rate.

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